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146 条记录 (耗时 0.021 秒)

    Charge pump system with smooth voltage output
    1.
    发明授权
    Charge pump system with smooth voltage output 有权

    公开(公告)号：US07224207B2

    公开(公告)日：2007-05-29

    申请号：US11231035

    申请日：2005-09-20

    申请人： Chung-Cheng Chou ,  Chien-Hua Huang

    发明人： Chung-Cheng Chou ,  Chien-Hua Huang

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07

    摘要： A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output voltage and controlling the charge pump for stabilizing the output voltage.

    Circuit and method for self-refresh of DRAM cells through monitoring of cell leakage currents
    2.
    发明授权
    Circuit and method for self-refresh of DRAM cells through monitoring of cell leakage currents 有权
    通过监测电池漏电流来自动刷新DRAM单元的电路和方法

    公开(公告)号：US06862239B1

    公开(公告)日：2005-03-01

    申请号：US10696291

    申请日：2003-10-29

    申请人： Chien-Hua Huang ,  Chung-Cheng Chou

    发明人： Chien-Hua Huang ,  Chung-Cheng Chou

    IPC分类号： G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4068

    摘要： A circuit and a method for self refresh of DRAM cells are provided. The circuit comprises a bias generator and an oscillator. The bias generator comprises a first current generator, a second current generator and a converter. The first current generator generates a first leakage current of “0” state cells. The second current generator generates a second leakage current of “1” state cells. The converter transforms a current comprising the first leakage current and the second leakage current into output biases. The method comprises generating leakage currents from memory cells; transforming the leakage currents into output biases for determining a self refresh period; and using the output biases to control an oscillator for generating a periodical signal pulse in response to the leakage currents.

    摘要翻译： 提供了一种用于DRAM单元的自刷新的电路和方法。 电路包括偏置发生器和振荡器。 偏置发生器包括第一电流发生器，第二电流发生器和转换器。 第一电流发生器产生“0”状态单元的第一泄漏电流。 第二电流发生器产生“1”状态单元的第二泄漏电流。 转换器将包括第一漏电流和第二漏电流的电流转换成输出偏压。 该方法包括从存储器单元产生泄漏电流; 将泄漏电流转换成输出偏压，以确定自刷新周期; 以及使用所述输出偏压来控制用于响应于所述漏电流产生周期性信号脉冲的振荡器。

    Charge pump system with smooth voltage output
    4.
    发明申请
    Charge pump system with smooth voltage output 有权
    电荷泵系统，电压输出平滑

    公开(公告)号：US20070063761A1

    公开(公告)日：2007-03-22

    申请号：US11231035

    申请日：2005-09-20

    申请人： Chung-Cheng Chou ,  Chien-Hua Huang

    发明人： Chung-Cheng Chou ,  Chien-Hua Huang

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07

    摘要： A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output voltage and controlling the charge pump for stabilizing the output voltage.

    摘要翻译： 公开了一种改进的电荷泵系统的方法和系统。 该系统包括用于提供输出电压的一个或多个电荷泵装置，与电荷泵装置耦合以提供振荡器输出的环形振荡器，以及用于检测输出电压并控制电荷泵稳定输出的多电平检测装置 电压。

    Dynamic random access memory cell leakage current detector
    5.
    发明申请
    Dynamic random access memory cell leakage current detector 有权
    动态随机存取存储单元泄漏电流检测器

    公开(公告)号：US20050248976A1

    公开(公告)日：2005-11-10

    申请号：US10840098

    申请日：2004-05-06

    申请人： Chien-Hua Huang ,  Chung-Cheng Chou

    发明人： Chien-Hua Huang ,  Chung-Cheng Chou

    IPC分类号： G11C7/12 ,  G11C11/24 ,  G11C11/4094 ,  G11C29/50

    CPC分类号： G11C29/50016 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/50

    摘要： A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.

    摘要翻译： 提供了可操作以测量动态随机存取存储器（DRAM）中的泄漏电流的电路，其包括耦合到公共位线，公共字线和公共存储节点的多个DRAM位单元存取晶体管，其中所述存取晶体管可以 被偏置以模拟DRAM的对应的多个非活动位单元; 以及与公共存储节点通信的电流镜，可操作以当存取晶体管被偏置以模拟非活动位单元时，来自所述多个位单元存取晶体管的总泄漏电流。

    Dynamic random access memory cell leakage current detector
    7.
    发明授权
    Dynamic random access memory cell leakage current detector 有权
    动态随机存取存储单元泄漏电流检测器

    公开(公告)号：US07035131B2

    公开(公告)日：2006-04-25

    申请号：US10840098

    申请日：2004-05-06

    申请人： Chien-Hua Huang ,  Chung-Cheng Chou

    发明人： Chien-Hua Huang ,  Chung-Cheng Chou

    IPC分类号： G11C11/24

    CPC分类号： G11C29/50016 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/50

    摘要： A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.

    摘要翻译： 提供了可操作以测量动态随机存取存储器（DRAM）中的泄漏电流的电路，其包括耦合到公共位线，公共字线和公共存储节点的多个DRAM位单元存取晶体管，其中所述存取晶体管可以 被偏置以模拟DRAM的对应的多个非活动位单元; 以及与公共存储节点通信的电流镜，可操作以当存取晶体管被偏置以模拟非活动位单元时，来自所述多个位单元存取晶体管的总泄漏电流。

    SRAM write assist apparatus
    8.
    发明授权
    SRAM write assist apparatus 有权
    SRAM写入辅助装置

    公开(公告)号：US08724420B2

    公开(公告)日：2014-05-13

    申请号：US13105382

    申请日：2011-05-11

    申请人： Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

    发明人： Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

    IPC分类号： G11C11/413

    CPC分类号： G11C11/419 ,  G11C11/41 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

    摘要： An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.

    摘要翻译： SRAM写入辅助装置包括定时器单元和分压器。 分压器单元被配置为将电压电位分压到较低电平。 在写入操作中，分压器的输出连接到存储单元。 定时器单元被配置为产生具有与施加到存储芯片的电压电位成反比的宽度的脉冲。 此外，定时器单元控制将来自分压器的输出的较低电压施加到存储单元的周期。 此外，可以使用外部电平和定时可编程信号来进一步调整分压器的比例和来自定时器单元的脉冲宽度。 通过采用SRAM写入辅助装置，存储器芯片可以执行可靠且快速的写入操作。

    Optical touch system and operating method thereof
    9.
    发明授权
    Optical touch system and operating method thereof 有权
    光触摸系统及其操作方法

    公开(公告)号：US08593414B2

    公开(公告)日：2013-11-26

    申请号：US12718658

    申请日：2010-03-05

    申请人： Meng-Shin Yen ,  William Wang ,  Chung-Cheng Chou

    发明人： Meng-Shin Yen ,  William Wang ,  Chung-Cheng Chou

    IPC分类号： G06F3/041

    CPC分类号： G06F3/0423 ,  G06F1/1643

    摘要： An optical touch system is disclosed. The optical touch system includes an optical touch apparatus, a control apparatus, and a rotating apparatus. When the control apparatus receives a mode switching signal, the control apparatus selects a corresponding specific using mode from a plurality of default using modes according to the mode switching signal. And, the specific using mode corresponds to a specific rotating angle. The rotating apparatus rotates the optical touch apparatus with the specific rotating angle to make the optical touch apparatus is rotated from a first location to a second location, so that a user can perform an input action via the optical touch apparatus according to the specific using mode.

    摘要翻译： 公开了一种光学触摸系统。 光学触摸系统包括光学触摸装置，控制装置和旋转装置。 当控制装置接收到模式切换信号时，控制装置根据模式切换信号从多个默认使用模式中选择对应的特定使用模式。 而且，具体使用模式对应于特定的旋转角度。 旋转装置以特定的旋转角旋转光学触摸装置，使得光学触摸装置从第一位置旋转到第二位置，使得用户可以根据特定的使用模式经由光学触摸装置执行输入动作 。

    Internal clock gating apparatus
    10.
    发明授权
    Internal clock gating apparatus 有权
    内部时钟选通装置

    公开(公告)号：US08575965B2

    公开(公告)日：2013-11-05

    申请号：US13118060

    申请日：2011-05-27

    申请人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

    发明人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

    IPC分类号： H03K19/096

    CPC分类号： G06F1/3287 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/171

    摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.

    摘要翻译： 内部时钟选通装置包括静态逻辑块和多米诺逻辑块。 静态逻辑块被配置为接收时钟信号和时钟使能信号。 多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。 静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。 另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。 此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。