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    Electrical fuse structure
    1.
    发明授权
    Electrical fuse structure 有权
    电熔丝结构

    公开(公告)号：US08026573B2

    公开(公告)日：2011-09-27

    申请号：US12335510

    申请日：2008-12-15

    申请人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  San-Fu Lin

    发明人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  San-Fu Lin

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.

    摘要翻译： 公开了电熔丝结构。 电熔丝结构包括设置在半导体衬底的表面上的熔丝元件，与熔丝元件的一端电连接的阴极以及与熔丝元件的另一端电连接的阳极。 具体而言，压电应力层设置在熔丝元件的至少一部分上。

    Phase change memory
    2.
    发明授权
    Phase change memory 有权
    相变记忆

    公开(公告)号：US08035097B2

    公开(公告)日：2011-10-11

    申请号：US12325801

    申请日：2008-12-01

    申请人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chien-Hsien Chen

    发明人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chien-Hsien Chen

    IPC分类号： H01L29/06 ,  H01L47/00

    CPC分类号： H01L45/06 ,  G11C5/063 ,  G11C13/0004 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

    摘要： A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.

    摘要翻译： 提供了一种相变存储器，其包括具有第一导电类型的半导体衬底，具有第二导电类型的埋入字线，具有第一导电类型的掺杂半导体层，存储单元，金属硅化物层和位线。 掩埋字线设置在半导体衬底中。 每个掩埋字线包括沿着第一方向延伸的线状主体部分和突出部分。 每个突起部分连接到线状主体部分的一个长边。 每个掺杂半导体层设置在一个突出部分上。 每个存储单元包括相变材料层，并且被布置在一个掺杂半导体层上并与其电连接。 每个金属硅化物层设置在一个线状主要部分上。 每个位线以基本上垂直于第一方向的第二方向连接到设置在字线上的存储单元。

    PHASE CHANGE MEMORY
    4.
    发明申请
    PHASE CHANGE MEMORY 有权
    相变记忆

    公开(公告)号：US20100133503A1

    公开(公告)日：2010-06-03

    申请号：US12325801

    申请日：2008-12-01

    申请人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chien-Hsien Chen

    发明人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chien-Hsien Chen

    IPC分类号： H01L45/00 ,  G11C11/00

    CPC分类号： H01L45/06 ,  G11C5/063 ,  G11C13/0004 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

    摘要： A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.

    摘要翻译： 提供了一种相变存储器，其包括具有第一导电类型的半导体衬底，具有第二导电类型的埋入字线，具有第一导电类型的掺杂半导体层，存储单元，金属硅化物层和位线。 掩埋字线设置在半导体衬底中。 每个掩埋字线包括沿着第一方向延伸的线状主体部分和突出部分。 每个突起部分连接到线状主体部分的一个长边。 每个掺杂半导体层设置在一个突出部分上。 每个存储单元包括相变材料层，并且被布置在一个掺杂半导体层上并与其电连接。 每个金属硅化物层设置在一个线状主要部分上。 每个位线以基本上垂直于第一方向的第二方向连接到设置在字线上的存储单元。

    ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME
    6.
    发明申请
    ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
    电熔丝结构及其制造方法

    公开(公告)号：US20100148915A1

    公开(公告)日：2010-06-17

    申请号：US12335510

    申请日：2008-12-15

    申请人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  San-Fu Lin

    发明人： Chien-Li Kuo ,  Yung-Chang Lin ,  Kuei-Sheng Wu ,  San-Fu Lin

    IPC分类号： H01H85/04

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.

    摘要翻译： 公开了电熔丝结构。 电熔丝结构包括设置在半导体衬底的表面上的熔丝元件，与熔丝元件的一端电连接的阴极以及与熔丝元件的另一端电连接的阳极。 具体而言，压电应力层设置在熔丝元件的至少一部分上。

    Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse
    9.
    发明授权
    Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse 有权
    形成电熔丝和金属栅晶体管及相关电熔丝的方法

    公开(公告)号：US08227890B2

    公开(公告)日：2012-07-24

    申请号：US12641322

    申请日：2009-12-18

    申请人： Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chang-Chien Wong

    发明人： Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chang-Chien Wong

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.

    摘要翻译： 本发明提供了一种将电熔丝工艺集成到高k /金属栅极工艺中的方法。 该方法同时形成晶体管的虚拟栅极堆叠和电子熔丝的虚拟栅极堆叠; 并且同时去除晶体管区域中的虚拟栅极堆叠的多晶硅和电子熔丝区域中的伪栅极堆叠的多晶硅。 此后，去除设置在电熔丝区域的开口中的功函数金属层; 并且晶体管区域中的开口和具有金属导电结构的e熔丝区域中的开口被填充以形成晶体管的电熔丝和金属栅极。

    Method of fabricating efuse, resistor and transistor
    10.
    发明授权
    Method of fabricating efuse, resistor and transistor 有权
    制造efuse，电阻和晶体管的方法

    公开(公告)号：US08071437B2

    公开(公告)日：2011-12-06

    申请号：US12621518

    申请日：2009-11-19

    申请人： Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chang-Chien Wong ,  Ching-Hsiang Tseng

    发明人： Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chang-Chien Wong ,  Ching-Hsiang Tseng

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/7848

    摘要： A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.

    摘要翻译： 一种制造efuse，电阻器和晶体管的方法包括以下步骤：提供衬底。 然后，在衬底上形成栅极，电阻器和efuse，其中栅极，电阻器和efuse一起包括第一介电层，多晶硅层和硬掩模。 之后，在栅极之外的基板中形成源极/漏极掺杂区域。 之后，去除电阻和efuse中的硬掩模。 随后，执行自对准硅化处理以在源/漏掺杂区域，电阻器和efuse上形成硅化物层。 然后，在基板上形成平坦化的第二介质层，露出栅极中的多晶硅。 之后，去除栅极中的多晶硅以形成凹陷。 最后，形成一个金属层以填充凹槽。