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    Method Of Making High-Voltage MOS Transistors With Thin Poly Gate
    1.
    发明申请
    Method Of Making High-Voltage MOS Transistors With Thin Poly Gate 审中-公开
    制造具有薄多孔栅极的高压MOS晶体管的方法

    公开(公告)号：US20140273387A1

    公开(公告)日：2014-09-18

    申请号：US13839533

    申请日：2013-03-15

    申请人： Chien-Sheng Su ,  Jeng-Wei Yang ,  Mandana Tadayoni ,  Yueh-Hsin Chen

    发明人： Chien-Sheng Su ,  Jeng-Wei Yang ,  Mandana Tadayoni ,  Yueh-Hsin Chen

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66477 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method of forming an MOS transistor by forming a poly gate over and insulated from a substrate, forming a layer of protective insulation material on the poly gate, and then performing a first implant of dopant material into portions of the substrate adjacent the poly gate, wherein the layer of protective insulation material and the poly gate block most or all of the first implant from reaching a portion of the substrate underneath the poly gate. One or more spacers are then formed adjacent the poly gate, followed by a second implant of dopant material into portions of the substrate adjacent to the one or more spacers.

    摘要翻译： 一种形成MOS晶体管的方法，该方法是在多晶硅栅极上形成保护绝缘材料层，然后在邻近多晶硅栅极的基板的第一部分中进行第一次掺杂， 其中所述保护绝缘材料层和所述多晶硅栅极阻挡所述第一注入的大部分或全部到达所述多晶硅栅极下方的所述衬底的一部分。 然后在多晶硅栅极附近形成一个或多个间隔物，随后将掺杂剂材料第二次注入到与该一个或多个间隔物相邻的衬底的部分中。

    Method of forming a memory cell by reducing diffusion of dopants under a gate
    4.
    发明授权
    Method of forming a memory cell by reducing diffusion of dopants under a gate 有权
    通过减少栅极下掺杂剂的扩散形成存储单元的方法

    公开(公告)号：US08785307B2

    公开(公告)日：2014-07-22

    申请号：US13593448

    申请日：2012-08-23

    申请人： Xian Liu ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    发明人： Xian Liu ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    IPC分类号： H01L21/04

    CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

    摘要翻译： 形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极 一侧的浮动门。 在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于 九十度，大于零度。

    Split-gate memory cell with substrate stressor region, and method of making same
    5.
    发明授权
    Split-gate memory cell with substrate stressor region, and method of making same 有权
    具有衬底应力区域的分离栅存储单元及其制造方法

    公开(公告)号：US09018690B2

    公开(公告)日：2015-04-28

    申请号：US13631490

    申请日：2012-09-28

    申请人： Mandana Tadayoni ,  Nhan Do

    发明人： Mandana Tadayoni ,  Nhan Do

    IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28 ,  H01L27/115

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/1054 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/788

    摘要： A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

    摘要翻译： 一种存储器件及其制造方法，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，导电浮动 栅极覆盖并与衬底绝缘，其中浮置栅极至少部分地布置在第一区域和通道区域的第一部分之上，导电第二栅极横向邻近并与浮动栅极绝缘，其中第二栅极被布置 至少部分地覆盖并与沟道区的第二部分绝缘，以及形成在第二栅极下方的衬底中的嵌入碳化硅的应力区域。

    Split-Gate Memory Cell With Substrate Stressor Region, And Method Of Making Same
    6.
    发明申请
    Split-Gate Memory Cell With Substrate Stressor Region, And Method Of Making Same 有权
    具有基板应力区域的分离门存储单元及其制作方法

    公开(公告)号：US20140091382A1

    公开(公告)日：2014-04-03

    申请号：US13631490

    申请日：2012-09-28

    申请人： Mandana Tadayoni ,  Nhan Do

    发明人： Mandana Tadayoni ,  Nhan Do

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/1054 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/788

    摘要： A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

    摘要翻译： 一种存储器件及其制造方法，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，导电浮动 栅极覆盖并与衬底绝缘，其中浮置栅极至少部分地布置在第一区域和通道区域的第一部分之上，导电第二栅极横向邻近并与浮动栅极绝缘，其中第二栅极被布置 至少部分地覆盖并与沟道区的第二部分绝缘，以及形成在第二栅极下方的衬底中的嵌入碳化硅的应力区域。

    Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate
    7.
    发明申请
    Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate 有权
    使用耦合栅极操作分离栅极闪存单元的方法

    公开(公告)号：US20130121085A1

    公开(公告)日：2013-05-16

    申请号：US13463558

    申请日：2012-05-03

    申请人： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'Mani

    发明人： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'Mani

    IPC分类号： G11C16/26

    CPC分类号： G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    摘要： A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    摘要翻译： 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

    Method of operating a split gate flash memory cell with coupling gate
    8.
    发明授权
    Method of operating a split gate flash memory cell with coupling gate 有权
    操作具有耦合栅极的分离栅极闪存单元的方法

    公开(公告)号：US08711636B2

    公开(公告)日：2014-04-29

    申请号：US13463558

    申请日：2012-05-03

    申请人： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'Mani

    发明人： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'Mani

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    摘要： A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    摘要翻译： 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。