公开(公告)号：US20060134899A1

公开(公告)日：2006-06-22

申请号：US10905185

申请日：2004-12-21

申请人： Chih-Ning Wu ,  Charlie CJ Lee ,  Kuan-Yang Liao

发明人： Chih-Ning Wu ,  Charlie CJ Lee ,  Kuan-Yang Liao

IPC分类号： H01L21/461

CPC分类号： H01L29/7843 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.

摘要翻译： 在晶片上形成MOS晶体管之后去除间隔物的方法。 MOS晶体管包括设置在衬底上的栅极，设置在栅极的侧壁上的间隔物以及衬垫旁边的源极和漏极区域。 通过在黑暗中执行湿式蚀刻工艺来去除间隔物，使得在间隔物去除工艺期间，可以防止MOS晶体管中的源极和漏极区域损坏。

公开(公告)号：US07595234B2

公开(公告)日：2009-09-29

申请号：US11532100

申请日：2006-09-15

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US20070066041A1

公开(公告)日：2007-03-22

申请号：US11532100

申请日：2006-09-15

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： H01L21/4763

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US07214988B2

公开(公告)日：2007-05-08

申请号：US11162693

申请日：2005-09-20

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： H01L29/76

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US07196019B2

公开(公告)日：2007-03-27

申请号：US10905185

申请日：2004-12-21

申请人： Chih-Ning Wu ,  Charlie C J Lee ,  Kuan-Yang Liao

发明人： Chih-Ning Wu ,  Charlie C J Lee ,  Kuan-Yang Liao

IPC分类号： H01L21/302

CPC分类号： H01L29/7843 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.

摘要翻译： 在晶片上形成MOS晶体管之后去除间隔物的方法。 MOS晶体管包括设置在衬底上的栅极，设置在栅极的侧壁上的间隔物以及衬垫旁边的源极和漏极区域。 通过在黑暗中执行湿式蚀刻工艺来去除间隔物，使得在间隔物去除工艺期间，可以防止MOS晶体管中的源极和漏极区域损坏。

公开(公告)号：US20060172548A1

公开(公告)日：2006-08-03

申请号：US11050261

申请日：2005-02-02

申请人： Chih-Ning Wu ,  Charlie Lee ,  Kuan-Yang Liao

发明人： Chih-Ning Wu ,  Charlie Lee ,  Kuan-Yang Liao

IPC分类号： H01L21/336 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02071 ,  H01L21/0206 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

摘要： A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.

摘要翻译： 一种适用于图案化栅极结构的清洁晶片的方法。 栅极结构包括依次层叠在衬底上的栅极介电层，含氮势垒层和含硅栅极层。 该方法包括用磷酸溶液和氢氟酸溶液清洗基板，使得可以除去在含氮阻挡层和含硅栅层之间的反应中形成的氮化硅残留物，并且可以减少污染物和颗粒的量 。 最终，改善了工艺的产量以及设备的质量和可靠性。

公开(公告)号：US20060110688A1

公开(公告)日：2006-05-25

申请号：US10993593

申请日：2004-11-19

申请人： Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： G03F7/36

CPC分类号： G03F7/405 ,  G03F7/40

摘要： An etching process compatible with DUV lithography is described. A mask layer is previously formed over a material layer to be etched through a DUV lithography process of 193 nm or 157 nm. Then, plasma etching is performed to pattern the material layer using the mask layer as an etching mask, wherein the etching gas causes a protective layer to form on the surface of the mask layer. The etching gas of the plasma etching includes at least a halogen-containing gas and Xe, wherein the halogen can be F, Cl, Br or a combination thereof.

摘要翻译： 描述了与DUV光刻相兼容的蚀刻工艺。 预先通过193nm或157nm的DUV光刻工艺在待蚀刻的材料层上形成掩模层。 然后，进行等离子体蚀刻，使用掩模层作为蚀刻掩模对材料层进行图案化，其中蚀刻气体在掩模层的表面上形成保护层。 等离子体蚀刻的蚀刻气体至少包含含卤素的气体和Xe，其中卤素可以是F，Cl，Br或其组合。

公开(公告)号：US07220647B2

公开(公告)日：2007-05-22

申请号：US11050261

申请日：2005-02-02

申请人： Chih-Ning Wu ,  Charlie C J Lee ,  Kuan-Yang Liao

发明人： Chih-Ning Wu ,  Charlie C J Lee ,  Kuan-Yang Liao

IPC分类号： H01L21/336 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02071 ,  H01L21/0206 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

摘要： A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.

摘要翻译： 一种适用于图案化栅极结构的清洁晶片的方法。 栅极结构包括依次层叠在衬底上的栅极介电层，含氮势垒层和含硅栅极层。 该方法包括用磷酸溶液和氢氟酸溶液清洗基板，使得可以除去在含氮阻挡层和含硅栅层之间的反应中形成的氮化硅残留物，并且可以减少污染物和颗粒的量 。 最终，改善了工艺的产量以及设备的质量和可靠性。

公开(公告)号：US20070063290A1

公开(公告)日：2007-03-22

申请号：US11162693

申请日：2005-09-20

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

公开(公告)号：US20080057655A1

公开(公告)日：2008-03-06

申请号：US11936093

申请日：2007-11-07

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。