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14 条记录 (耗时 0.026 秒)

    Profile pre-shaping for replacement poly gate interlayer dielectric
    1.
    发明授权
    Profile pre-shaping for replacement poly gate interlayer dielectric 有权
    轮廓预成型用于替代多晶硅层间电介质

    公开(公告)号：US08803249B2

    公开(公告)日：2014-08-12

    申请号：US13570527

    申请日：2012-08-09

    申请人： Chih-Wei Chiang ,  Kuang-Cheng Wu ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    发明人： Chih-Wei Chiang ,  Kuang-Cheng Wu ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    IPC分类号： H01L29/78

    CPC分类号： H01L21/28132 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/66545

    摘要： Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

    摘要翻译： 一些实施例涉及集成电路（IC）。 IC包括具有上表面的半导体衬底，源表面和漏区附近。 在源极区域和漏极区域之间的衬底中设置沟道区域。 栅电极设置在沟道区上方并通过栅极电介质与沟道区分离。 侧壁间隔件围绕栅电极的相对侧壁形成。 侧壁间隔件的上外边缘向外延伸超过侧壁间隔件的相应的下外边缘。 衬套设置在侧壁间隔物的相对侧壁周围，并且在衬垫的上部具有第一厚度，在衬垫的下部具有第二厚度。 第一厚度小于第二厚度。 还公开了其他实施例。

    INTERLAYER DIELECTRIC STRUCTURE AND METHOD MAKING THE SAME
    4.
    发明申请
    INTERLAYER DIELECTRIC STRUCTURE AND METHOD MAKING THE SAME 有权
    中间层介电结构及其制备方法

    公开(公告)号：US20130043539A1

    公开(公告)日：2013-02-21

    申请号：US13212904

    申请日：2011-08-18

    申请人： Jen-Chi Chang ,  Chun-Li Lin ,  Kai-Shiung Hsu ,  Ming-Shiou Kuo ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    发明人： Jen-Chi Chang ,  Chun-Li Lin ,  Kai-Shiung Hsu ,  Ming-Shiou Kuo ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871

    摘要： The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

    摘要翻译： 本公开提供了制造集成电路的方法。 该方法包括在半导体衬底上形成栅叠层; 在栅极堆叠和半导体衬底上形成应力接触蚀刻停止层（CESL）; 在大于约440℃的沉积温度下使用高纵横比法（HARP）在应力CESL上形成第一介电材料层以驱出氢氧化物（OH）基团; 在所述第一介电材料层上形成第二介电材料层; 蚀刻以在第一和第二介电材料层中形成接触孔; 用导电材料填充接触孔; 并进行化学机械抛光（CMP）工艺。

    Low temperature method for minimizing copper hillock defects
    8.
    发明申请
    Low temperature method for minimizing copper hillock defects 有权
    用于最小化铜小丘缺陷的低温方法

    公开(公告)号：US20060252258A1

    公开(公告)日：2006-11-09

    申请号：US11122393

    申请日：2005-05-05

    申请人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    发明人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/76801 ,  H01L21/76883

    摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200 ° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

    摘要翻译： 公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。 低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。 小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。 在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

    Low temperature method for minimizing copper hillock defects
    9.
    发明授权
    Low temperature method for minimizing copper hillock defects 有权
    用于最小化铜小丘缺陷的低温方法

    公开(公告)号：US07851358B2

    公开(公告)日：2010-12-14

    申请号：US11122393

    申请日：2005-05-05

    申请人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    发明人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/76801 ,  H01L21/76883

    摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

    摘要翻译： 公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。 低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。 小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。 在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。