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    INTERLAYER DIELECTRIC STRUCTURE AND METHOD MAKING THE SAME
    2.
    发明申请
    INTERLAYER DIELECTRIC STRUCTURE AND METHOD MAKING THE SAME 有权
    中间层介电结构及其制备方法

    公开(公告)号：US20130043539A1

    公开(公告)日：2013-02-21

    申请号：US13212904

    申请日：2011-08-18

    申请人： Jen-Chi Chang ,  Chun-Li Lin ,  Kai-Shiung Hsu ,  Ming-Shiou Kuo ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    发明人： Jen-Chi Chang ,  Chun-Li Lin ,  Kai-Shiung Hsu ,  Ming-Shiou Kuo ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871

    摘要： The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

    摘要翻译： 本公开提供了制造集成电路的方法。 该方法包括在半导体衬底上形成栅叠层; 在栅极堆叠和半导体衬底上形成应力接触蚀刻停止层（CESL）; 在大于约440℃的沉积温度下使用高纵横比法（HARP）在应力CESL上形成第一介电材料层以驱出氢氧化物（OH）基团; 在所述第一介电材料层上形成第二介电材料层; 蚀刻以在第一和第二介电材料层中形成接触孔; 用导电材料填充接触孔; 并进行化学机械抛光（CMP）工艺。

    Profile pre-shaping for replacement poly gate interlayer dielectric
    3.
    发明授权
    Profile pre-shaping for replacement poly gate interlayer dielectric 有权
    轮廓预成型用于替代多晶硅层间电介质

    公开(公告)号：US08803249B2

    公开(公告)日：2014-08-12

    申请号：US13570527

    申请日：2012-08-09

    申请人： Chih-Wei Chiang ,  Kuang-Cheng Wu ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    发明人： Chih-Wei Chiang ,  Kuang-Cheng Wu ,  Wen-Long Lee ,  Po-Hsiung Leu ,  Ding-I Liu

    IPC分类号： H01L29/78

    CPC分类号： H01L21/28132 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/66545

    摘要： Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

    摘要翻译： 一些实施例涉及集成电路（IC）。 IC包括具有上表面的半导体衬底，源表面和漏区附近。 在源极区域和漏极区域之间的衬底中设置沟道区域。 栅电极设置在沟道区上方并通过栅极电介质与沟道区分离。 侧壁间隔件围绕栅电极的相对侧壁形成。 侧壁间隔件的上外边缘向外延伸超过侧壁间隔件的相应的下外边缘。 衬套设置在侧壁间隔物的相对侧壁周围，并且在衬垫的上部具有第一厚度，在衬垫的下部具有第二厚度。 第一厚度小于第二厚度。 还公开了其他实施例。

    Apparatus for Dielectric Deposition Process
    6.
    发明申请
    Apparatus for Dielectric Deposition Process 有权
    电介质沉积工艺设备

    公开(公告)号：US20140026813A1

    公开(公告)日：2014-01-30

    申请号：US13557904

    申请日：2012-07-25

    申请人： Lan-Hai Wang ,  Ding-I Liu ,  Si-Wen Liao ,  Po-Hsiung Leu ,  Yong-Hung Yang

    发明人： Lan-Hai Wang ,  Ding-I Liu ,  Si-Wen Liao ,  Po-Hsiung Leu ,  Yong-Hung Yang

    IPC分类号： C23C16/455 ,  C23C16/50

    CPC分类号： C23C16/401 ,  C23C16/4557 ,  C23C16/45574 ,  C23C16/50

    摘要： An apparatus comprises a first gas inlet coupled between a first pipe and a reaction chamber, wherein the first pipe configured to carry process gases, a second gas inlet coupled between a second pipe and the reaction chamber, wherein the second pipe configured to carry a precursor material in a gaseous state and a heating device coupled to the second pipe and the second gas inlet, wherein the heating device keeps an ambient temperature of the second pipe and the second gas inlet above a boiling point of the precursor material.

    摘要翻译： 一种装置包括耦合在第一管和反应室之间的第一气体入口，其中第一管被构造成承载处理气体，第二气体入口连接在第二管和反应室之间，其中第二管配置成承载前体 处于气态的材料和耦合到第二管和第二气体入口的加热装置，其中加热装置将第二管和第二气体入口的环境温度保持在前体材料的沸点之上。

    Mechanism of patterning a semiconductor device and product resulting therefrom
    8.
    发明授权
    Mechanism of patterning a semiconductor device and product resulting therefrom 有权
    图案化半导体器件的机理及由此产生的产品

    公开(公告)号：US08884404B2

    公开(公告)日：2014-11-11

    申请号：US13409931

    申请日：2012-03-01

    申请人： Yi-Fang Li ,  Chun-Li Lin ,  Chun-Sheng Wu ,  Ding-I Liu

    发明人： Yi-Fang Li ,  Chun-Li Lin ,  Chun-Sheng Wu ,  Ding-I Liu

    IPC分类号： H01L29/02

    CPC分类号： H01L21/76898 ,  H01L21/3086

    摘要： The description relates to a method of patterning a semiconductor device to create a through substrate via. The method produces a through substrate via having no photoresist material therein. An intermediate layer deposited over an interlayer dielectric prevents etching solutions from etching interlayer dielectric sidewalls to prevent peeling. The description relates to a semiconductor apparatus including a semiconductor substrate having a through substrate via therein. The semiconductor apparatus further includes an interlayer dielectric over the semiconductor substrate and an intermediate layer over semiconductor substrate and over sidewalls of the interlayer dielectric.

    摘要翻译： 该描述涉及图案化半导体器件以形成直通衬底通孔的方法。 该方法通过在其中没有光致抗蚀剂材料产生通孔基板。 沉积在层间电介质上的中间层防止蚀刻溶液蚀刻层间电介质侧壁以防止剥离。 该描述涉及包括其中具有通孔基板的半导体基板的半导体装置。 该半导体装置还包括位于半导体衬底上的层间电介质以及半导体衬底上的中间层以及层间电介质的侧壁。