公开(公告)号：US07611589B2

公开(公告)日：2009-11-03

申请号：US11072114

申请日：2005-03-04

申请人： Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B08B3/02 ,  B08B1/04

CPC分类号： B08B1/04 ,  B08B3/02 ,  H01L21/67051

摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

摘要翻译： 旋转晶片清洗的方法。 该方法包括控制旋转速度和垂直喷水压力。 垂直喷射压力和旋转速度基本保持成反比例。 晶圆转速在50至1200rpm之间。 垂直晶片喷射压力为0.05至100KPa。

公开(公告)号：US20060196526A1

公开(公告)日：2006-09-07

申请号：US11072114

申请日：2005-03-04

申请人： Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23G1/00 ,  B08B7/00 ,  B08B3/00

CPC分类号： B08B1/04 ,  B08B3/02 ,  H01L21/67051

摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

公开(公告)号：US07635651B2

公开(公告)日：2009-12-22

申请号：US11208612

申请日：2005-08-23

申请人： Wen-Long Lee ,  Jun Wu ,  Shih-Chi Lin ,  Chyi-Tsong Ni

发明人： Wen-Long Lee ,  Jun Wu ,  Shih-Chi Lin ,  Chyi-Tsong Ni

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31051 ,  H01L21/31053

摘要： A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

摘要翻译： 一种平滑电介质层的方法。 首先，提供基板。 接下来，在半导体衬底上形成电介质层。 最后，通过使用硅烷类气体和氮气体气体的等离子体处理使介电层平滑化。

公开(公告)号：US20060252258A1

公开(公告)日：2006-11-09

申请号：US11122393

申请日：2005-05-05

申请人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

发明人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76801 ,  H01L21/76883

摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200 ° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

摘要翻译： 公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。 低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。 小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。 在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

公开(公告)号：US07851358B2

公开(公告)日：2010-12-14

申请号：US11122393

申请日：2005-05-05

申请人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

发明人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76801 ,  H01L21/76883

摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

摘要翻译： 公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。 低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。 小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。 在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

公开(公告)号：US20060189149A1

公开(公告)日：2006-08-24

申请号：US11208612

申请日：2005-08-23

申请人： Wen-Long Lee ,  Jun Wu ,  Shih-Chi Lin ,  Chyi-Tsong Ni

发明人： Wen-Long Lee ,  Jun Wu ,  Shih-Chi Lin ,  Chyi-Tsong Ni

IPC分类号： H01L21/31

CPC分类号： H01L21/31051 ,  H01L21/31053

摘要： A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

公开(公告)号：US06979656B2

公开(公告)日：2005-12-27

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

摘要翻译： 制造电介质层的方法提供了当形成碳和卤素掺杂的硅酸盐玻璃介电层时与卤素源材料分开的碳源材料的使用。 当形成碳和卤素掺杂的硅酸盐玻璃介电层时，使用单独的碳和卤素源材料提供了增强的工艺自由度。 具有大于约3.0的介电常数的这种碳和卤素掺杂的硅酸盐玻璃介电层特别适用于镶嵌法中的本征平面化停止层。 包含碳和卤素掺杂的硅酸盐玻璃的双层电介质层结构和不含卤素掺杂的碳掺杂的硅酸盐玻璃介电层在双镶嵌方法中是有用的。

公开(公告)号：US20050121751A1

公开(公告)日：2005-06-09

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

公开(公告)号：US06352924B1

公开(公告)日：2002-03-05

申请号：US09587463

申请日：2000-06-05

申请人： Jun Wu ,  Ming Jer Lee ,  Yu Ku Lin ,  Ying-Lang Wang

发明人： Jun Wu ,  Ming Jer Lee ,  Yu Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L2144

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877

摘要： A new method is provided to replace tungsten plugs for wafers that trigger the WCVD backside alarm. In this new rework process, the original TiN glue layer is sputter etched back and a new (“fresh”) 100-Angstrom thick layer of TiN is deposited. The new tungsten plug is created over the top surface of the refreshed glue layer.

摘要翻译： 提供了一种新方法来替代触发WCVD背面报警的晶片的钨丝塞。 在这种新的返工过程中，将原始TiN胶层溅射回蚀刻，并沉积出新的（“新鲜”）100埃厚的TiN层。 新的钨丝塞在刷新的胶层的上表面上形成。

公开(公告)号：US06291872B1

公开(公告)日：2001-09-18

申请号：US09433255

申请日：1999-11-04

申请人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

发明人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01L27/08

摘要： Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.

摘要翻译： 公开了集成电路电感器的垂直型结构。 这些垂直型电感器包括在本发明中形成三个不同实施例的单环型，并联环型和螺旋型。 在第一实施例中，采用单环型的三维型结构作为集成电路电感器。 该电感器结构形成在基板上，并且该结构的轴线垂直于基板。 在根据本发明的另一实施例中，提供了一种用于射频（RF）集成电路电感器的并联环路结构。 根据本发明的螺杆型结构是第三实施例。 它具有平行于衬底表面并进入半导体器件的轴线。