公开(公告)号：US06429425B1

公开(公告)日：2002-08-06

申请号：US09340402

申请日：1999-06-28

申请人： Chih-Yung Lin ,  Jiunn-Ren Hwang

发明人： Chih-Yung Lin ,  Jiunn-Ren Hwang

IPC分类号： G12B1300

CPC分类号： G01B15/00 ,  G01B3/30 ,  G03F7/00 ,  H01J2237/2817

摘要： The invention relates to a method for adjusting a micro-bar of an electron microscope to increase the accuracy of the micro-bar. The method entails first forming a photo-resist layer on a semiconductor wafer, and exposing a predetermined region of the photo-resist layer to a light of a specific wavelength. Then, a resist stripping process is performed to remove the photo-resist layer in the predetermined region. The periphery of the predetermined region of the photo-resist layer will form a vertical side wall with a periodic wave shape similar to a sine wave, and the wavelength of the periodic wave shape is determined by the wavelength of the light and the refraction rate of the photo-resist layer. Finally, the micro-bar of the electron microscope is adjusted using the wavelength of the periodic wave shape on the vertical side wall.

摘要翻译： 本发明涉及一种用于调整电子显微镜的微型棒以提高微型棒的精度的方法。 该方法首先在半导体晶片上形成光致抗蚀剂层，并将光刻胶层的预定区域曝光到特定波长的光。 然后，进行抗蚀剂剥离处理以除去预定区域中的光致抗蚀剂层。 光致抗蚀剂层的预定区域的周边将形成与正弦波相似的周期波形的垂直侧壁，并且周期波形的波长由光的波长和折射率决定 光刻胶层。 最后，使用垂直侧壁上的周期波形的波长调整电子显微镜的微条。

公开(公告)号：US07847335B2

公开(公告)日：2010-12-07

申请号：US11402529

申请日：2006-04-11

申请人： Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

发明人： Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.

摘要翻译： 非易失性半导体存储器件包括形成在衬底，半导体间隔物，氧化物 - 氮化物 - 氧化物堆叠和接触焊盘上的栅堆叠。 半导体间隔物邻近栅极堆叠的两侧并在衬底上方。 氧化物 - 氧化物 - 氧化物堆叠位于间隔物和栅极堆叠之间，并且位于间隔物和衬底之间，使得氧化物 - 氧化物 - 氧化物堆叠在至少一侧上具有大致L形的横截面 门堆叠。 接触垫在栅极电极和半导体间隔物之间​​是电接触的。 接触焊盘可以进一步形成在栅电极和半导体间隔物之间​​的氧化物 - 氮化物 - 氧化物堆叠的凹陷部分。 接触焊盘可以包括其上形成有金属硅化物的外延硅。

公开(公告)号：US07663134B2

公开(公告)日：2010-02-16

申请号：US11775741

申请日：2007-07-10

申请人： Tzyh-Cheang Lee ,  Chun-Sheng Liang ,  Jiunn-Ren Hwang ,  Fu-Liang Yang

发明人： Tzyh-Cheang Lee ,  Chun-Sheng Liang ,  Jiunn-Ren Hwang ,  Fu-Liang Yang

IPC分类号： H01L47/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/78 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

摘要： An array includes a transistor cpmprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.

摘要翻译： 阵列包括：晶体管，包括第一端子，第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元，具有第一端和第二端，其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元，其中所述第三端连接到所述第二接触插塞。

公开(公告)号：US07589387B2

公开(公告)日：2009-09-15

申请号：US11243771

申请日：2005-10-05

申请人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

发明人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

IPC分类号： H01L27/088

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42348 ,  H01L29/785 ,  H01L29/7923

摘要： A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a gate electrode on the gate insulation film, and two charge-trapping regions along opposite sides of the gate electrode, wherein each charge-trapping region is separated from the gate electrode and the semiconductor fin by a tunneling layer. The memory cell further includes a protective layer on the charge-trapping regions. Each of the two charge-trapping regions is capable of storing one bit. The memory cell can be operated by applying different bias voltages to the source, the drain, and the gate of the memory cell.

摘要翻译： 提供能够存储2位的2位FinFET闪存单元及其形成方法。 存储单元包括在衬底的顶表面上的半导体鳍片，顶表面上的栅极绝缘膜和半导体鳍片的沟道部分的侧壁，栅极绝缘膜上的栅电极和沿着两个电荷捕获区域 栅电极的相对侧，其中每个电荷俘获区域通过隧道层与栅极电极和半导体鳍片分离。 存储单元还包括在电荷捕获区上的保护层。 两个电荷捕获区域中的每一个能够存储一个位。 可以通过向存储器单元的源极，漏极和栅极施加不同的偏置电压来操作存储器单元。

公开(公告)号：US07297450B2

公开(公告)日：2007-11-20

申请号：US11380192

申请日：2006-04-25

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03F9/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US20070161195A1

公开(公告)日：2007-07-12

申请号：US11327185

申请日：2006-01-06

申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S438/954

摘要： A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.

摘要翻译： 提供了一种用于侧壁SONOS存储器件的系统和方法。 电子设备包括非易失性存储器。 衬底包括源极/漏极区域。 栅极堆叠直接在衬底上并且在源极/漏极区域之间。 栅极堆叠具有侧壁。 在栅叠层附近形成氮化物间隔物。 第一氧化物材料直接邻近间隔物形成。 在间隔物和栅极叠层之间形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构在栅极堆叠的至少一侧具有大致L形的横截面。 氧化物 - 氮化物 - 氧化物结构包括垂直部分和水平部分。 垂直部分基本上与侧壁对准并且位于第一氧化物材料和栅极侧壁之间。 水平部分基本上与衬底对准并位于第一氧化物和衬底之间。

公开(公告)号：US20050009344A1

公开(公告)日：2005-01-13

申请号：US10711198

申请日：2004-09-01

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03F1/00 ,  G03F1/14 ,  H01L21/302 ,  H01L21/461

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US06391757B1

公开(公告)日：2002-05-21

申请号：US09875508

申请日：2001-06-06

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Yeong-Song Yen ,  Ching-Hsu Chang

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Yeong-Song Yen ,  Ching-Hsu Chang

IPC分类号： H01L2144

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031

摘要： A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.

摘要翻译： 双镶嵌工艺包括在半导体晶片的衬底上形成第一钝化层，第一介电层和第二钝化层。 执行第一光刻和蚀刻工艺以在第二钝化层和第一介电层中形成至少一个通孔。 此后，在半导体晶片的表面上形成第二电介质层和第三钝化层，随后进行第二光刻和蚀刻工艺，以在第三钝化层和第二介电层中形成至少一个沟槽。 沟槽和通孔一起构成双镶嵌结构。 最后，在半导体晶片的表面上形成阻挡层和金属层，进行化学机械抛光（CMP）工艺以完成双镶嵌工艺。

公开(公告)号：US06337269B1

公开(公告)日：2002-01-08

申请号：US09885042

申请日：2001-06-21

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76804 ,  H01L21/76813

摘要： The present invention fabricates a dual damascene structure. A passivation layer, a first dielectric layer, a second passivation layer, a second dielectric layer, a third passivation layer and a third dielectric layer are formed on the surface of the semiconductor wafer followed by etching the third dielectric layer to form a pattern of an upper trench of the dual damascene structure. Then the third passivation layer and the second dielectric layer are etched down to the surface of the second passivation layer so as to form a pattern of a via hole of the dual damascene structure. Thereafter, the third passivation layer and the second passivation layer not covered by the third dielectric layer and the second dielectric layer are removed. The third dielectric layer and the second passivation layer are used as hard masks to remove the second dielectric layer and the first dielectric layer until the surface of the first passivation layer. Finally, the second passivation layer and the first passivation layer not covered by the second dielectric layer and the first dielectric layer are removed to the surface of the conductive layer so completing the process of fabricating the dual damascene structure.

摘要翻译： 本发明制造双镶嵌结构。 在半导体晶片的表面上形成钝化层，第一介电层，第二钝化层，第二介电层，第三钝化层和第三介电层，然后蚀刻第三介电层，形成图案 双层镶嵌结构的上沟槽。 然后，将第三钝化层和第二介电层向下蚀刻到第二钝化层的表面，以形成双镶嵌结构的通孔的图案。 此后，除去未被第三电介质层和第二电介质层覆盖的第三钝化层和第二钝化层。 第三介电层和第二钝化层用作硬掩模以去除第二介电层和第一介电层直到第一钝化层的表面。 最后，将第二钝化层和未被第二介电层和第一介电层覆盖的第一钝化层除去到导电层的表面，从而完成制造双镶嵌结构的工艺。

公开(公告)号：US08618610B2

公开(公告)日：2013-12-31

申请号：US12651029

申请日：2009-12-31

申请人： Li-Ting Wang ,  Jiunn-Ren Hwang

发明人： Li-Ting Wang ,  Jiunn-Ren Hwang

IPC分类号： H01L21/70

CPC分类号： H01L21/324 ,  H01L27/0207 ,  H01L27/11

摘要： The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.

摘要翻译： 本公开提供了一种半导体结构，其包括具有器件区域和邻近器件区域的虚设区域的半导体衬底; 所述器件区域中的多个有源区; 以及所述虚拟区域中的多个虚拟有源区域，其中所述有源区域中的每一个具有在第一方向上的第一尺寸和与所述第一方向垂直的第二方向上的第二尺寸，并且所述第一尺寸基本上大于所述第二尺寸 尺寸; 并且所述虚拟有源区域中的每一个具有在所述第一方向上的第三尺寸和在所述第二方向上的第四尺寸，并且所述第三尺寸基本上大于所述第四尺寸。 多个虚拟有源区域被配置为使得虚拟区域中的热退火效应基本上等于器件区域的热退火效果。