公开(公告)号：US08238501B2

公开(公告)日：2012-08-07

申请号：US12266530

申请日：2008-11-06

申请人： Ching Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

发明人： Ching Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

IPC分类号： H04L7/033

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0041 ,  H04L7/0087 ,  H04Q11/0067 ,  H04Q2011/0079

摘要： A burst-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.

摘要翻译： 提供了使用相位选择技术的突发模式时钟和数据恢复电路。 在数据恢复电路中，使用锁相环（PLL）电路来提供多个具有时钟相位的固定时钟信号。 过采样相位选择电路耦合到锁相环电路，用于通过使用时钟信号检测接收数据信号的数据沿，并根据数据沿的位置选择要锁定的时钟相位。 延迟锁定回路（DLL）电路耦合到锁相环电路和过采样相位选择电路，并用于将数据信号的数据相位与所选择的时钟信号的时钟相位进行比较，以便延迟 数据信号的数据相位延迟一个延迟时间，直到数据相位被锁定为时钟相位。

公开(公告)号：US20120163794A1

公开(公告)日：2012-06-28

申请号：US13191983

申请日：2011-07-27

申请人： Jung Mao LIN ,  Ching Yuan Yang

发明人： Jung Mao LIN ,  Ching Yuan Yang

IPC分类号： H04J14/00 ,  H03K5/00

CPC分类号： H03K5/1534 ,  H04L7/0338

摘要： A level transition determination circuit includes a multi-phase clock generator, an oversampling unit, and a state detection circuit. The multi-phase clock generator is used for receiving an input clock signal and generating S×N clock signals, in which S and N are integers. Each clock signal is synchronized to the input clock signal and has a different delay time. The oversampling unit is used for performing N-times oversampling on M bit periods of the serial input data according to the clock signals, so as to generate M×N sampled values in parallel during the M bit periods. The state detection circuit is used for receiving (M×N)+1 sampled values and generating N detection signals by detecting level transitions between adjacent sampled values of the (M×N)+1 sampled values and the level transition results.

摘要翻译： 电平转换确定电路包括多相时钟发生器，过采样单元和状态检测电路。 多相时钟发生器用于接收输入时钟信号并产生S×N个时钟信号，其中S和N是整数。 每个时钟信号与输入时钟信号同步并具有不同的延迟时间。 过采样单元用于根据时钟信号对串行输入数据的M位周期进行N次过采样，以便在M位周期期间并行生成M×N采样值。 状态检测电路用于通过检测（M×N）+1采样值的相邻采样值和电平转换结果之间的电平转换来接收（M×N）+1采样值并产生N个检测信号。

公开(公告)号：US08615063B2

公开(公告)日：2013-12-24

申请号：US13191983

申请日：2011-07-27

申请人： Jung Mao Lin ,  Ching Yuan Yang

发明人： Jung Mao Lin ,  Ching Yuan Yang

IPC分类号： H04L7/00

CPC分类号： H03K5/1534 ,  H04L7/0338

摘要： A level transition determination circuit includes a multi-phase clock generator, an oversampling unit, and a state detection circuit. The multi-phase clock generator is used for receiving an input clock signal and generating S×N clock signals, in which S and N are integers. Each clock signal is synchronized to the input clock signal and has a different delay time. The oversampling unit is used for performing N-times oversampling on M bit periods of the serial input data according to the clock signals, so as to generate M×N sampled values in parallel during the M bit periods. The state detection circuit is used for receiving (M×N)+1 sampled values and generating N detection signals by detecting level transitions between adjacent sampled values of the (M×N)+1 sampled values and the level transition results.

摘要翻译： 电平转换确定电路包括多相时钟发生器，过采样单元和状态检测电路。 多相时钟发生器用于接收输入时钟信号并产生S×N个时钟信号，其中S和N是整数。 每个时钟信号与输入时钟信号同步并具有不同的延迟时间。 过采样单元用于根据时钟信号对串行输入数据的M位周期进行N次过采样，以便在M位周期期间并行生成M×N采样值。 状态检测电路用于通过检测（M×N）+1采样值的相邻采样值和电平转换结果之间的电平转换来接收（M×N）+1采样值并产生N个检测信号。