公开(公告)号：US07005339B2

公开(公告)日：2006-02-28

申请号：US10707444

申请日：2003-12-15

申请人： Ching-Chun Huang ,  Ming-Hsien Huang ,  Rong-Ching Chen ,  Jy-Hwang Lin

发明人： Ching-Chun Huang ,  Ming-Hsien Huang ,  Rong-Ching Chen ,  Jy-Hwang Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/76229 ,  H01L21/823418 ,  H01L21/823456

摘要： The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.

摘要翻译： 本发明提供一种将至少一个高电压金属氧化物半导体器件和至少一个亚微米金属氧化物半导体器件集成在衬底上的方法。 该方法包括：提供衬底，在衬底的表面上形成具有不同深度的多个浅沟槽，以及形成填充浅沟槽的多个氧化硅层，并且每个氧化硅层的顶部处于 蘑菇的形状。

公开(公告)号：US20050130378A1

公开(公告)日：2005-06-16

申请号：US10707444

申请日：2003-12-15

申请人： Ching-Chun Huang ,  Ming-Hsien Huang ,  Rong-Ching Chen ,  Jy-Hwang Lin

发明人： Ching-Chun Huang ,  Ming-Hsien Huang ,  Rong-Ching Chen ,  Jy-Hwang Lin

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/823418 ,  H01L21/823456

摘要： The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.

摘要翻译： 本发明提供一种将至少一个高电压金属氧化物半导体器件和至少一个亚微米金属氧化物半导体器件集成在衬底上的方法。 该方法包括：提供衬底，在衬底的表面上形成具有不同深度的多个浅沟槽，以及形成填充浅沟槽的多个氧化硅层，并且每个氧化硅层的顶部处于 蘑菇的形状。

公开(公告)号：US06900097B2

公开(公告)日：2005-05-31

申请号：US10435018

申请日：2003-05-12

申请人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

发明人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/981

摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

摘要翻译： 首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中 第一井和第二井用于分离高压装置，第一井的深度与第二井相同。 此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极 在位于单电平EEPROM的浮置栅极的第二部分的第三阱中，其中高压器件可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

公开(公告)号：USRE44156E1

公开(公告)日：2013-04-16

申请号：US11391667

申请日：2006-03-29

申请人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

发明人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

IPC分类号： H01L21/02 ,  H01L21/336

CPC分类号： H01L27/11526 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11546

摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

摘要翻译： 首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中 第一井和第二井用于分离高压装置，第一井的深度与第二井相同。 此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极 位于单电平EEPROM的浮置栅极的第二部分下方的第三阱中，其中高电压装置可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

公开(公告)号：US20130147967A1

公开(公告)日：2013-06-13

申请号：US13476120

申请日：2012-05-21

申请人： Yu-Fen Tsai ,  Ching-Chun Huang

发明人： Yu-Fen Tsai ,  Ching-Chun Huang

IPC分类号： H04N17/00

CPC分类号： H04N17/04

摘要： A testing apparatus for a television system is provided. The testing apparatus includes an analysis module, a signal generating module, a transmitting module, a receiving module, and a judging module. The analysis module receives and analyzes a control signal to generate an analysis result.The signal generating module generates a test signal according to the analysis result. The transmitting module transmits the test signal to the television system. The receiving module receives a response signal from the television system. The judging module judges whether the response signal correctly corresponds to the test signal.

摘要翻译： 提供一种用于电视系统的测试装置。 测试装置包括分析模块，信号产生模块，发送模块，接收模块和判断模块。 分析模块接收并分析控制信号以生成分析结果。 信号生成模块根据分析结果生成测试信号。 发送模块将测试信号发送到电视系统。 接收模块从电视系统接收响应信号。 判断模块判断响应信号是否正确对应于测试信号。

公开(公告)号：US08059864B2

公开(公告)日：2011-11-15

申请号：US12111190

申请日：2008-04-28

申请人： Ching-Chun Huang ,  Yao-Jen Chang ,  Ruei-Cheng Wu ,  Cheng-Peng Kuan

发明人： Ching-Chun Huang ,  Yao-Jen Chang ,  Ruei-Cheng Wu ,  Cheng-Peng Kuan

IPC分类号： G06K9/00

CPC分类号： G08G1/14 ,  G06K9/00785 ,  G06K9/6277 ,  G06K9/6296

摘要： Disclosed is a system and method of image-based space detection. The system includes an image selection module, a 3-layer detection mechanism and an optimization module. At least one image processing area that may affect space-status judgment is selected from plural image processing areas. The 3-layer detection mechanism having an observation layer, a labeling layer, and a semantic layer observes the information about the selected image processing area, associates with a local classification model, and adjacent local constraint model and a global semantics model to completely describe the probability distribution of the links among the three layers, and provide global label constraint information. The optimization module analyzes the probability distribution and global label constraint information, and generates an image-based optimized space detection result.

摘要翻译： 公开了基于图像的空间检测的系统和方法。 该系统包括图像选择模块，3层检测机构和优化模块。 从多个图像处理区域中选择可能影响空间状态判断的至少一个图像处理区域。 具有观察层，标记层和语义层的3层检测机构观察关于所选图像处理区域的信息，与本地分类模型相关联，以及相邻局部约束模型和全局语义模型，以完全描述 在三层之间的链路的概率分布，并提供全局标签约束信息。 优化模块分析概率分布和全局标签约束信息，并生成基于图像的优化空间检测结果。

公开(公告)号：US20070256106A1

公开(公告)日：2007-11-01

申请号：US11798199

申请日：2007-05-11

申请人： Wen-Ming Huang ,  Chi-Wei Hsiao ,  Wen-Fu Tsai ,  Ching-Chun Huang ,  Hsin-Ching Yin ,  Chi-Hsien Wang ,  Ching-Lai Tsai

发明人： Wen-Ming Huang ,  Chi-Wei Hsiao ,  Wen-Fu Tsai ,  Ching-Chun Huang ,  Hsin-Ching Yin ,  Chi-Hsien Wang ,  Ching-Lai Tsai

IPC分类号： H04N7/18

CPC分类号： H04N21/42607 ,  H04N19/132 ,  H04N19/188 ,  H04N19/46 ,  H04N19/61 ,  H04N19/91 ,  H04N21/4363 ,  H04N21/4385

摘要： A controller for filtering sub-channels of DVB is provided, including a media access control (MAC) unit, at least a data compression unit and at least a physical interface circuit. The MAC unit includes a plurality of registers. The MAC unit is connected to the DVB packets through a bus, and the registers provide storage for the program identification of at least one DVB sub-channel packet so that the MAC unit can determine whether to discard or output the DVB packet based on the program identification. The data compression unit is connected to MAC unit for being controlled to determine whether the packet should be compressed before output. The physical interface circuit is connected to the MAC unit and the data compression unit for outputting the compressed or uncompressed packets.

摘要翻译： 提供了一种用于过滤DVB的子信道的控制器，包括媒体接入控制（MAC）单元，至少一个数据压缩单元和至少一个物理接口电路。 MAC单元包括多个寄存器。 MAC单元通过总线连接到DVB分组，并且寄存器为至少一个DVB子信道分组的节目标识提供存储，使得MAC单元可以基于该程序确定是丢弃还是输出DVB分组 识别。 数据压缩单元连接到MAC单元以进行控制，以确定在输出之前是否应该压缩分组。 物理接口电路连接到MAC单元和数据压缩单元，用于输出压缩或未压缩的数据包。

公开(公告)号：US20100135006A1

公开(公告)日：2010-06-03

申请号：US12591330

申请日：2009-11-17

申请人： Ching-Chun Huang

发明人： Ching-Chun Huang

IPC分类号： F21L4/00

CPC分类号： F21V11/06 ,  F21S8/02 ,  F21S8/06 ,  F21V19/001 ,  F21V19/04 ,  F21Y2115/10

摘要： An LED light group lamp includes a plurality of fixing portions criss-crossed and equidistantly disposed at a front side of a lamp holder, and a power supply module, installed at a back side of the lamp holder and electrically coupled to each fixing portion, and each LED light source is soldered, inserted, latched or screwed to the fixing portion, and the lamp holder includes a protective cover at a front side of the lamp holder. The modular design of the lamp not just significantly reduces the manufacturing cost only, but also facilitates the installation of the lamp to a general ceiling or a light steel frame as well as its maintenance and repair. Each LED light source can be replaced separately to lower the application cost, and the heat produced by each LED light source can be dissipated through the lamp holder and the fixture body to enhance the lifetime of the lamp.

摘要翻译： LED灯组灯包括多个固定部分，其交叉并等距设置在灯座的前侧;以及电源模块，其安装在灯座的背面并电耦合到每个固定部分，以及 每个LED光源被焊接，插入，锁定或螺纹连接到固定部分，并且灯座包括在灯座前侧的保护盖。 灯的模块化设计不仅显着降低了制造成本，而且还有助于将灯安装到通用天花板或轻钢框架以及其维护和修理。 每个LED光源可以单独更换以降低应用成本，并且每个LED光源产生的热量可以通过灯座和灯具体消散，以增加灯的寿命。

公开(公告)号：US20090085772A1

公开(公告)日：2009-04-02

申请号：US12111190

申请日：2008-04-28

申请人： Ching-Chun Huang ,  Yao-Jen Chang ,  Ruei-Cheng Wu ,  Cheng-Peng Kuan

发明人： Ching-Chun Huang ,  Yao-Jen Chang ,  Ruei-Cheng Wu ,  Cheng-Peng Kuan

IPC分类号： G08G1/14

CPC分类号： G08G1/14 ,  G06K9/00785 ,  G06K9/6277 ,  G06K9/6296

摘要： Disclosed is a system and method of image-based space detection. The system includes an image selection module, a 3-layer detection mechanism and an optimization module. At least one image processing area that may affect space-status judgment is selected from plural image processing areas. The 3-layer detection mechanism having an observation layer, a labeling layer, and a semantic layer observes the information about the selected image processing area, associates with a local classification model, and adjacent local constraint model and a global semantics model to completely describe the probability distribution of the links among the three layers, and provide global label constraint information. The optimization module analyzes the probability distribution and global label constraint information, and generates an image-based optimized space detection result.

摘要翻译： 公开了基于图像的空间检测的系统和方法。 该系统包括图像选择模块，3层检测机构和优化模块。 从多个图像处理区域中选择可能影响空间状态判断的至少一个图像处理区域。 具有观察层，标记层和语义层的3层检测机构观察关于所选择的图像处理区域的信息，与本地分类模型相关联，以及相邻的局部约束模型和全局语义模型，以完全描述 在三层之间的链路的概率分布，并提供全局标签约束信息。 优化模块分析概率分布和全局标签约束信息，并生成基于图像的优化空间检测结果。

公开(公告)号：US06242315B1

公开(公告)日：2001-06-05

申请号：US09186126

申请日：1998-11-04

申请人： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

发明人： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

IPC分类号： H01L2120

CPC分类号： H01L28/55 ,  H01L21/76838 ,  H01L28/60

摘要： A method of manufacturing the metallic electrodes of a capacitor in a mixed mode semiconductor device. The method comprises the steps of providing a substrate having a conductive layer and the lower electrode of a capacitor formed thereon, and then depositing a dielectric layer over the substrate. A first opening and a second opening are then formed in the dielectric layer. The first opening exposes a portion of the conductive layer while the second opening exposes a portion of the lower electrode. Finally, a conductive plug and the upper electrode of the capacitor are formed in the respective first and second openings that are in corresponding positions above the conductive layer and lower electrode, respectively.

摘要翻译： 一种在混合模式半导体器件中制造电容器的金属电极的方法。 该方法包括以下步骤：提供具有导电层和形成在其上的电容器的下电极的衬底，然后在衬底上沉积介电层。 然后在电介质层中形成第一开口和第二开口。 第一开口暴露导电层的一部分，而第二开口暴露下部电极的一部分。 最后，分别在导电层和下电极上方的相应位置的相应的第一和第二开口中形成导电插塞和电容器的上电极。