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    Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage
    1.
    再颁专利
    Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage 有权
    用于在具有高/低压环境的环境中操作的单级电可擦除和可编程只读存储器的形成方法

    公开(公告)号：USRE44156E1

    公开(公告)日：2013-04-16

    申请号：US11391667

    申请日：2006-03-29

    申请人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

    发明人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

    IPC分类号： H01L21/02 ,  H01L21/336

    CPC分类号： H01L27/11526 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11546

    摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

    摘要翻译： 首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中 第一井和第二井用于分离高压装置，第一井的深度与第二井相同。 此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极 位于单电平EEPROM的浮置栅极的第二部分下方的第三阱中，其中高电压装置可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

    Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage
    4.
    发明授权
    Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage 有权
    用于在具有高/低压环境的环境中操作的单级电可擦除和可编程只读存储器的形成方法

    公开(公告)号：US06900097B2

    公开(公告)日：2005-05-31

    申请号：US10435018

    申请日：2003-05-12

    申请人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

    发明人： Rong-Ching Chen ,  Ching-Chun Huang ,  Jy-Hwang Lin

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/981

    摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

    摘要翻译： 首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中 第一井和第二井用于分离高压装置，第一井的深度与第二井相同。 此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极 在位于单电平EEPROM的浮置栅极的第二部分的第三阱中，其中高压器件可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

    Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-Voltage
    5.
    发明申请
    Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-Voltage 审中-公开
    在高/低电压环境下形成单级电可擦除可编程只读存储器的方法

    公开(公告)号：US20100240181A1

    公开(公告)日：2010-09-23

    申请号：US12789364

    申请日：2010-05-27

    申请人： Rong-Ching CHEN ,  Ching-Chun HUANG ,  Jy-Hwang LIN

    发明人： Rong-Ching CHEN ,  Ching-Chun HUANG ,  Jy-Hwang LIN

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/981

    摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

    摘要翻译： 首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中 第一井和第二井用于分离高压装置，第一井的深度与第二井相同。 此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极 位于单电平EEPROM的浮置栅极的第二部分下方的第三阱中，其中高电压装置可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

    Method for improving the dimple phenomena of a polysilicon film deposited on a trench
    6.
    发明授权
    Method for improving the dimple phenomena of a polysilicon film deposited on a trench 有权
    改善沉积在沟槽上的多晶硅膜的凹坑现象的方法

    公开(公告)号：US06335260B1

    公开(公告)日：2002-01-01

    申请号：US09627136

    申请日：2000-07-27

    申请人： Mao-song Tseng ,  Rong-ching Chen ,  Chin-lin Lin ,  Su-wen Chang

    发明人： Mao-song Tseng ,  Rong-ching Chen ,  Chin-lin Lin ,  Su-wen Chang

    IPC分类号： H01L2176

    CPC分类号： H01L21/763 ,  G03F1/36

    摘要： In the invention, a photoresist layer is first spread on a semiconductor structure, and then using a photomask with a specially designed pattern exposes the photoresist layer. Next, the photoresist layer is developed to form a patterned photoresist layer. Thereafter, using the patterned photoresist layer as a mask, a trench is formed in the semiconductor structure by selective etching. The pattern of the photomask according to the invention is formed as in the following steps. At first, a first pattern extending in a first direction and having a first side and a second side that is opposite to the first side is formed. Next, a second pattern extending in a second direction that is perpendicular to the first direction is formed in such a way that an end of the second pattern is connected with the first side of the first pattern. Thereafter, a concave edge is formed on the second side to substantially face the second pattern. The distance between the first side and the second side is shortened due to the presence of the concave edge. As a result, the depth of the dimples developed at the intersection points of the dimple lines is greatly reduced when a polysilicon layer is deposited on the trench formed according to the invention.

    摘要翻译： 在本发明中，光致抗蚀剂层首先在半导体结构上扩散，然后使用具有特殊设计图案的光掩模曝光光刻胶层。 接下来，将光致抗蚀剂层显影以形成图案化的光致抗蚀剂层。 此后，使用图案化的光致抗蚀剂层作为掩模，通过选择性蚀刻在半导体结构中形成沟槽。 根据本发明的光掩模的图案如以下步骤形成。 首先，形成沿第一方向延伸并具有与第一侧相反的第一侧和第二侧的第一图案。 接下来，沿着与第一方向垂直的第二方向延伸的第二图案形成为使得第二图案的端部与第一图案的第一侧连接。 此后，在第二侧上形成基本上面对第二图案的凹形边缘。 第一侧和第二侧之间的距离由于存在凹形边缘而缩短。 结果，当在根据本发明形成的沟槽上沉积多晶硅层时，在凹坑线的交点处产生的凹坑的深度大大减小。

    Self-aligned contact for trench DMOS transistors
    7.
    发明授权
    Self-aligned contact for trench DMOS transistors 有权
    沟槽DMOS晶体管的自对准接触

    公开(公告)号：US06184092B2

    公开(公告)日：2001-02-06

    申请号：US09444988

    申请日：1999-11-23

    申请人： Mao-song Tseng ,  Rong-ching Chen ,  Su-wen Chang ,  Chin-lin Lin

    发明人： Mao-song Tseng ,  Rong-ching Chen ,  Su-wen Chang ,  Chin-lin Lin

    IPC分类号： H01L21336

    摘要： A method for forming a self-aligned contact for a trench DMOS transistor comprises: providing a semiconductor substrate; etching a trench into the semiconductor substrate at a selected location on the surface of the semiconductor substrate; forming a first dielectric layer that covers the semiconductor substrate and walls of the trench; forming a plug in the trench, which comprises a step of depositing a semiconductor layer that covers the semiconductor substrate and fills in the trench, and a step of etching the semiconductor layer until the plug is below the trench for about 0.2 to 0.3 micron; forming a second dielectric layer on the plug; and forming a conductive layer over the second dielectric layer and the surface of the semiconductor substrate for ohmic contact regions.

    摘要翻译： 用于形成沟槽DMOS晶体管的自对准接触的方法包括：提供半导体衬底; 在所述半导体衬底的表面上的选定位置处将沟槽蚀刻到所述半导体衬底中; 形成覆盖半导体衬底和沟槽壁的第一介电层; 在沟槽中形成插塞，其包括沉积覆盖半导体衬底并填充在沟槽中的半导体层的步骤，以及蚀刻半导体层直到插塞在沟槽下方约0.2至0.3微米的步骤; 在所述插头上形成第二电介质层; 以及在第二电介质层和用于欧姆接触区域的半导体衬底的表面上形成导电层。