公开(公告)号：US20050030789A1

公开(公告)日：2005-02-10

申请号：US10707562

申请日：2003-12-22

申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475

摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

摘要翻译： 一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到 写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压 连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层 注入，并且将衬底电压施加到多个存储单元的衬底。

公开(公告)号：US06801456B1

公开(公告)日：2004-10-05

申请号：US10707474

申请日：2003-12-17

申请人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Jih-Wen Chou ,  Cheng-Tung Huang

发明人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Jih-Wen Chou ,  Cheng-Tung Huang

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C16/0466

摘要： A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P+ poly gate formed on the ONO stack layer, a P+ doped source region disposed in the N-well at one side of the gate, and a P+ doped drain region disposed in the N-well at the other side of the gate. The method includes the steps of: applying a word line voltage VWL on the P+ poly gate, applying a source line voltage VSL on the source, wherein the source line voltage VSL is greater than the word line voltage VWL, thereby providing adequate bias to turn on the P channel thereof. A bit line voltage that is smaller than the source line voltage VSL is applied on the P+ doped drain region, thereby driving channel hot holes to flow toward the P+ doped drain region and then inducing hot electron injection near the drain side. A well voltage VNW is applied to the N-well, wherein VNW=VSL.

摘要翻译： 公开了一种通过通道热载流子诱发的热电子注入机制来编程PMOS单晶体管闪存单元的方法。 PMOS单晶体管闪存单元包括位于半导体衬底的N阱上的ONO堆叠层，形成在ONO堆叠层上的P +多晶硅栅极，设置在N + 并且在栅极的另一侧设置在N阱中的P +掺杂漏极区。 该方法包括以下步骤：在P ++多栅极上施加字线电压VWL，在源极上施加源极线电压VSL，其中源极线电压VSL大于字线电压VWL，从而提供足够的 偏置以打开其P通道。 小于源极线电压VSL的位线电压施加在P +掺杂漏极区域上，从而驱动通道热孔流向P +掺杂漏极区域，然后在漏极附近引入热电子注入 侧。 将井电压VNW施加到N阱，其中VNW = VSL。

公开(公告)号：US06952369B2

公开(公告)日：2005-10-04

申请号：US10707562

申请日：2003-12-22

申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475

摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

摘要翻译： 一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到 写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压 连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层 注入，并且将衬底电压施加到多个存储单元的衬底。

公开(公告)号：US07531438B2

公开(公告)日：2009-05-12

申请号：US11491137

申请日：2006-07-24

申请人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

IPC分类号： H01L21/3205

CPC分类号： H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78 ,  Y10S438/981

摘要： A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

摘要翻译： 提供一种制造凹槽通道晶体管的方法。 首先，在掺杂半导体层和基板上形成硬掩模。 蚀刻掺杂半导体层和衬底以形成沟槽并且在掺杂半导体层中限定源极/漏极。 在沟槽的侧壁上以倾斜角度执行植入工艺以形成植入区域。 进行热氧化处理以形成氧化物层。 氧化物层包括在沟槽的侧壁中的源极/漏极上的第一厚度和在沟槽的侧壁中的另一部分上的第二厚度。

公开(公告)号：US06787419B2

公开(公告)日：2004-09-07

申请号：US10248363

申请日：2003-01-14

申请人： Chung-Yi Chen ,  Jih-Wen Chou ,  Chih-Hsun Chu

发明人： Chung-Yi Chen ,  Jih-Wen Chou ,  Chih-Hsun Chu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/11573

摘要： A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

摘要翻译： 晶片具有限定有第一区域和第二区域的基板。 依次在基板上形成ONO层，第一硅层和氮化硅层。 然后去除设置在第二区域上的ONO层，第一硅层和氮化硅层。 在第二区域上形成至少一个栅极氧化物层，并且在晶片上沉积第二硅层。 之后，进行光蚀刻处理以去除第一区域上的第二硅层和氮化硅层。 在晶片上形成至少第三硅层。 然后执行光蚀刻工艺和多个离子注入工艺以在衬底上形成每个MOS晶体管的栅极，漏极和源极。

公开(公告)号：US20070249123A1

公开(公告)日：2007-10-25

申请号：US11491137

申请日：2006-07-24

申请人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu ,  Hsiu-Chuan Shu

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/3205

CPC分类号： H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78 ,  Y10S438/981

摘要： A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

摘要翻译： 提供一种制造凹槽通道晶体管的方法。 首先，在掺杂半导体层和基板上形成硬掩模。 蚀刻掺杂半导体层和衬底以形成沟槽并且在掺杂半导体层中限定源极/漏极。 在沟槽的侧壁上以倾斜角度执行植入工艺以形成植入区域。 进行热氧化处理以形成氧化物层。 氧化物层包括在沟槽的侧壁中的源极/漏极上的第一厚度和在沟槽的侧壁中的另一部分上的第二厚度。

公开(公告)号：US20070012994A1

公开(公告)日：2007-01-18

申请号：US11162727

申请日：2005-09-21

申请人： Jih-Wen Chou ,  Chih-Hsun Chu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/0653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

摘要翻译： 提供半导体器件。 半导体器件具有栅极结构，源极区，漏极区和一对介电阻挡层。 栅极结构形成在基板上。 源极区域和漏极区域形成在栅极结构旁边的衬底中，并且在栅极结构之下的源极区域和漏极区域之间形成沟道区域。 一对电介质阻挡层分别形成在源极区域和漏极区域之间的栅极结构下方的衬底中。 电介质阻挡层用于在纳米级装置中降低漏极引发的阻挡层降低效果。

公开(公告)号：US07462545B2

公开(公告)日：2008-12-09

申请号：US11162727

申请日：2005-09-21

申请人： Jih-Wen Chou ,  Chih-Hsun Chu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

摘要翻译： 提供半导体器件。 半导体器件具有栅极结构，源极区，漏极区和一对介电阻挡层。 栅极结构形成在基板上。 源极区域和漏极区域形成在栅极结构旁边的衬底中，并且在栅极结构之下的源极区域和漏极区域之间形成沟道区域。 一对电介质阻挡层分别形成在源极区域和漏极区域之间的栅极结构下方的衬底中。 电介质阻挡层用于在纳米级装置中降低漏极引发的阻挡层降低效果。

公开(公告)号：US06228730B1

公开(公告)日：2001-05-08

申请号：US09301211

申请日：1999-04-28

申请人： Tung-Po Chen ,  Jih-Wen Chou

发明人： Tung-Po Chen ,  Jih-Wen Chou

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7834

摘要： A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

摘要翻译： 一种制造场效应晶体管的方法，其中提供具有栅极的基板。 衬套氧化物层和第一间隔件邻近栅极的侧面形成。 在衬底的栅极的两侧形成外延硅层，而在外延硅层下面的衬底中形成浅源极/漏极（S / D）延伸结。 形成氧化物层和第二间隔物以紧密地连接到第一间隔物并在外延硅层下面形成S / D区。 然后将外延硅层的一部分转变成金属硅化物层，以完成场效应晶体管的工艺。

公开(公告)号：US06200870B1

公开(公告)日：2001-03-13

申请号：US09189355

申请日：1998-11-09

申请人： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

发明人： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28061 ,  H01L21/28247

摘要： A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.

摘要翻译： 用于形成提高栅极质量的栅极的方法包括在衬底上顺序地形成栅极氧化物层，多晶硅层，导电层和掩模层。 此后，对掩模层，导电层，多晶硅层和栅极氧化物层进行图案化以形成栅极。 然后，通过用氮阳离子的离子注入，在导电层的侧壁上形成用于增加栅极的热稳定性和化学稳定性的钝化层。 氮阳离子通过离子注入在栅极氧化物层下方掺杂到衬底中，这可以改善磷离子的渗透。