公开(公告)号：US06914007B2

公开(公告)日：2005-07-05

申请号：US10366206

申请日：2003-02-13

申请人： Ching-Hui Ma ,  Chao-Cheng Chen ,  Tsang-Jiuh Wu ,  Hui-Chang Yu ,  Hun-Jan Tao

发明人： Ching-Hui Ma ,  Chao-Cheng Chen ,  Tsang-Jiuh Wu ,  Hui-Chang Yu ,  Hun-Jan Tao

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461 ,  H01L21/462

CPC分类号： H01J37/32009 ,  H01J2237/0206 ,  H01L21/31116 ,  H01L21/76802

摘要： A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CXFYHZ or a fluorocarbon and a gas such as O2, H2, N2, N2O, CO, CO2, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.

摘要翻译： 描述了一种减少衬底上的电荷以防止在后续蚀刻工艺中的电弧入射的方法。 图案化衬底被固定到处理室中的卡盘。 执行放电处理，其包括以下三个步骤：（a）将卡盘耦合到0伏连接，（b）产生等离子体，以及（c）将卡盘耦合到高压连接。 三个步骤以任何顺序进行。 在放电顺序期间，惰性气体或惰性气体和蚀刻气体流入腔室。 或者，碳氟化合物C 1 H Z，或碳氟化合物和气体如O 2 H，H N 2，N 2，N 2 O，CO，CO 2，He或Ar流入室 在放电序列期间。 该方法与批次或单晶片工艺兼容，并且可扩展到蚀刻导热性差的低k电介质层。

公开(公告)号：US06884728B2

公开(公告)日：2005-04-26

申请号：US10289972

申请日：2002-11-06

申请人： Jun-Lung Huang ,  Jen-Cheng Liu ,  Ching-Hui Ma ,  Yi-Chen Huang ,  Yin-Shen Chu ,  Hong-Ming Chen ,  Li-Chih Chaio

发明人： Jun-Lung Huang ,  Jen-Cheng Liu ,  Ching-Hui Ma ,  Yi-Chen Huang ,  Yin-Shen Chu ,  Hong-Ming Chen ,  Li-Chih Chaio

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

摘要翻译： 一种用于改善光刻图案化工艺以避免半导体制造工艺中未发展的光致抗蚀剂污染的方法，包括提供具有包括侧壁的各向异性蚀刻的开口的第一半导体特征。 第一半导体特征还提供光刻图案的上覆光致抗蚀剂层，以各向异性地蚀刻覆盖并包围第一半导体特征的第二半导体特征开口; 在所述覆盖的光致抗蚀剂层上方覆盖沉积聚合物钝化层，所述光致抗蚀剂层包括覆盖包括聚合物含有残余物的侧壁的至少一部分; 以及在各向异性蚀刻所述第二半导体特征之前，从所述侧壁的至少一部分去除所述聚合物钝化层，所述聚合物钝化层包括大部分含聚合物的残余物。

公开(公告)号：US06727183B1

公开(公告)日：2004-04-27

申请号：US09915842

申请日：2001-07-27

申请人： Ching-Hui Ma ,  Jen-Cheng Liu ,  Li-Chih Chao

发明人： Ching-Hui Ma ,  Jen-Cheng Liu ,  Li-Chih Chao

IPC分类号： H01L21302

CPC分类号： H01L21/76814 ,  H01L21/31116 ,  H01L21/76807

摘要： A novel etching method for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization is described. A region to be contacted is provided in or on a semiconductor substrate. A liner layer is deposited overlying the region to be contacted. An ultra low-k dielectric layer is deposited overlying the liner layer. A damascene opening is etched through the ultra low-k dielectric layer to the liner layer overlying the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, high power, and low pressure. The liner layer within the damascene opening is etched away to expose the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, low power, and low pressure to complete formation of a damascene opening in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种用于防止镶嵌金属化中的超低k材料层的尖锐和底切的新颖蚀刻方法。 待接触的区域设置在半导体衬底中或其上。 衬垫层被覆盖在待接触的区域上。 沉积在衬层上的超低k电介质层。 通过超低k电介质层将镶嵌开口蚀刻到覆盖待接触区域的衬垫层，其中该蚀刻包括高F / C比蚀刻化学，高功率和低压。 镶嵌开口内的衬里层被蚀刻掉以暴露待接触的区域，其中该蚀刻包括高F / C比蚀刻化学，低功率和低压，以在集成电路的制造中完成镶嵌开口的形成 设备。