公开(公告)号：US5767011A

公开(公告)日：1998-06-16

申请号：US749081

申请日：1996-11-14

申请人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

发明人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

IPC分类号： G06F17/50 ,  H01L23/528 ,  H01L21/28

CPC分类号： H01L23/5286 ,  G06F17/5077 ,  H01L2924/0002 ,  Y10S257/923

摘要： A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

摘要翻译： 一种用于通过集成电路制造互连的方法和结果。 该方法包括在高电流流动的区域附近添加更多的电力线80,100,1001和/或增加电力线120的宽度和/或增加电力总线140。 所得到的结构还在高电流流动的区域附近提供更多的金属化。 类似于该方法，所得到的结构可以包括额外的电力线80,100,1001和/或更宽的电力线120和/或电力总线140以增加金属化的量。 还提供了改进的路由技术。 这种路由技术包括提供初始Ucs值，然后在高电流区域附近添加附加线路以减小Ucs值。

公开(公告)号：US5923089A

公开(公告)日：1999-07-13

申请号：US816005

申请日：1997-03-10

申请人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

发明人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

IPC分类号： G06F17/50 ,  H01L23/528 ,  H01L23/48

CPC分类号： H01L23/5286 ,  G06F17/5077 ,  H01L2924/0002 ,  Y10S257/923

摘要： A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

摘要翻译： 一种用于通过集成电路制造互连的方法和结果。 该方法包括在高电流流动的区域附近添加更多的电力线80,100,1001和/或增加电力线120的宽度和/或增加电力总线140。 所得到的结构还在高电流流动的区域附近提供更多的金属化。 类似于该方法，所得到的结构可以包括额外的电力线80,100,1001和/或更宽的电力线120和/或电力总线140以增加金属化的量。 还提供了改进的路由技术。 这种路由技术包括提供初始Ucs值，然后在高电流区域附近添加附加线路以减小Ucs值。

公开(公告)号：US06201725B1

公开(公告)日：2001-03-13

申请号：US09592260

申请日：2000-06-12

申请人： Chingchi Yao ,  Chung-Jen Chien

发明人： Chingchi Yao ,  Chung-Jen Chien

IPC分类号： G11C502

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.

公开(公告)号：US6097048A

公开(公告)日：2000-08-01

申请号：US218303

申请日：1998-12-22

申请人： Chingchi Yao ,  Chung-Jen Chien ,  Thomas Chao

发明人： Chingchi Yao ,  Chung-Jen Chien ,  Thomas Chao

IPC分类号： H01L27/06 ,  H01L27/108

CPC分类号： H01L27/0629 ,  H01L27/108 ,  H01L27/10897

摘要： A dynamic random access memory (DRAM) cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors functions as a switch transistor while the other transistor is configured as a storage capacitor. The DRAM cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the DRAM cell may be fabricated in a logic device with the standard processes used to produce the logic device.

摘要翻译： 动态随机存取存储器（DRAM）单元包括第一和第二MOS晶体管，例如CMOS单元中的PMOS晶体管和NMOS晶体管。 两个晶体管中的一个用作开关晶体管，而另一个晶体管被配置为存储电容器。 可以使用形成在门阵列中的PMOS和NMOS晶体管单元将DRAM单元集成到诸如CMOS门阵列的逻辑器件中。 在这种情况下，可以使用用于产生逻辑器件的标准工艺在逻辑器件中制造DRAM单元。

公开(公告)号：US5838204A

公开(公告)日：1998-11-17

申请号：US712337

申请日：1996-09-11

申请人： Chingchi Yao

发明人： Chingchi Yao

IPC分类号： G06F1/10 ,  H01L27/118 ,  H03K3/03 ,  H03K19/177 ,  H03L7/089 ,  H03L7/099 ,  H03L7/00

CPC分类号： H03L7/0997 ,  G06F1/10 ,  H01L27/118 ,  H03K3/0315 ,  H01L2224/05554 ,  H03L7/0891

摘要： An application specific integrated circuit (ASIC) including a phase-locked loop (PLL) circuit operably coupled to an internal clock and an external clock. The present PLL circuit includes an internal phase detector circuit, an internal charge pump operably coupled to the phase detector circuit, a loop filter operably coupled to the charge pump, and an internal programmable voltage-controlled oscillator 200, 300. The internal programmable voltage controlled oscillator includes a plurality of delay elements, which have a respective switch to turn-on the delay elements. A storage device having a plurality of outputs providing selected switch signals to the voltage oscillator program one of a plurality of center frequencies. Each of the outputs is operably coupled respectively to the delay elements through the respective switch. The switch isolates a first group of delay elements from a second group of delay elements. Setting simultaneous operating (SSO) limits for an application specific integrated circuit (ASIC) having a phase-locked loop sets a limit for the PLL pins.

摘要翻译： 一种专用集成电路（ASIC），包括可操作地耦合到内部时钟和外部时钟的锁相环（PLL）电路。 本PLL电路包括内部相位检测器电路，可操作地耦合到相位检测器电路的内部电荷泵，可操作地耦合到电荷泵的环路滤波器和内部可编程压控振荡器200,3300。内部可编程电压控制 振荡器包括多个延迟元件，其具有相应的开关以接通延迟元件。 一种具有多个输出的存储装置，其将选择的开关信号提供给多个中心频率之一的电压振荡器程序。 每个输出通过相应的开关分别可操作地耦合到延迟元件。 该开关将第一组延迟元件与第二组延迟元件隔离。 为具有锁相环的专用集成电路（ASIC）设置同时工作（SSO）极限为PLL引脚设置极限。

公开(公告)号：US5646548A

公开(公告)日：1997-07-08

申请号：US601375

申请日：1996-02-14

申请人： Chingchi Yao ,  Poucheng Wang

发明人： Chingchi Yao ,  Poucheng Wang

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521 ,  H01L24/06 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.

摘要翻译： 半导体集成电路以多于一组VH / VL电压电平接收和发送信号。 集成电路包括核心区域，输入焊盘，输出焊盘，外围电路和多个电源线，每个电源线各自处于电源电压电平V1，V2，V3。 。 。 嗯 集成电路还包括输入电路和输出电路，每一个都具有缓冲器和转换器。 每个电源线的电源电压V1，V2，V3可用性。 。 。 Vm和转换器允许本电路在同一集成电路内传输和接收各种输入信号和输出信号。

公开(公告)号：US06215701B1

公开(公告)日：2001-04-10

申请号：US09218026

申请日：1998-12-22

申请人： Chingchi Yao ,  Chung-Jen Chien

发明人： Chingchi Yao ,  Chung-Jen Chien

IPC分类号： G11C1600

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.

摘要翻译： 非易失性存储单元包括第一和第二MOS晶体管，例如CMOS单元中的PMOS晶体管和NMOS晶体管。 两个晶体管之一提供用于存储数据的浮动栅极，而另一个晶体管设置有用于选择存储器单元的控制栅极，并且与用于读取存储在单元中的数据的位线连接。 非易失性存储单元可以使用形成在门阵列中的PMOS和NMOS晶体管单元集成到诸如CMOS门阵列的逻辑器件中。 在这种情况下，非易失性存储单元可以用用于产生逻辑器件的标准工艺制成逻辑器件。

公开(公告)号：US5521530A

公开(公告)日：1996-05-28

申请号：US299004

申请日：1994-08-31

申请人： Chingchi Yao ,  Poucheng Wang

发明人： Chingchi Yao ,  Poucheng Wang

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018521 ,  H01L24/06 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.

摘要翻译： 半导体集成电路以多于一组VH / VL电压电平接收和发送信号。 集成电路包括核心区域，输入焊盘，输出焊盘，外围电路和多个电源线，每个电源线各自处于电源电压电平V1，V2，V3。 。 。 嗯 集成电路还包括输入电路和输出电路，每一个都具有缓冲器和转换器。 每个电源线的电源电压V1，V2，V3可用性。 。 。 Vm和转换器允许本电路在同一集成电路内传输和接收各种输入信号和输出信号。