公开(公告)号：US5923089A

公开(公告)日：1999-07-13

申请号：US816005

申请日：1997-03-10

申请人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

发明人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

IPC分类号： G06F17/50 ,  H01L23/528 ,  H01L23/48

CPC分类号： H01L23/5286 ,  G06F17/5077 ,  H01L2924/0002 ,  Y10S257/923

摘要： A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

摘要翻译： 一种用于通过集成电路制造互连的方法和结果。 该方法包括在高电流流动的区域附近添加更多的电力线80,100,1001和/或增加电力线120的宽度和/或增加电力总线140。 所得到的结构还在高电流流动的区域附近提供更多的金属化。 类似于该方法，所得到的结构可以包括额外的电力线80,100,1001和/或更宽的电力线120和/或电力总线140以增加金属化的量。 还提供了改进的路由技术。 这种路由技术包括提供初始Ucs值，然后在高电流区域附近添加附加线路以减小Ucs值。

公开(公告)号：US5767011A

公开(公告)日：1998-06-16

申请号：US749081

申请日：1996-11-14

申请人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

发明人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

IPC分类号： G06F17/50 ,  H01L23/528 ,  H01L21/28

CPC分类号： H01L23/5286 ,  G06F17/5077 ,  H01L2924/0002 ,  Y10S257/923

摘要： A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

摘要翻译： 一种用于通过集成电路制造互连的方法和结果。 该方法包括在高电流流动的区域附近添加更多的电力线80,100,1001和/或增加电力线120的宽度和/或增加电力总线140。 所得到的结构还在高电流流动的区域附近提供更多的金属化。 类似于该方法，所得到的结构可以包括额外的电力线80,100,1001和/或更宽的电力线120和/或电力总线140以增加金属化的量。 还提供了改进的路由技术。 这种路由技术包括提供初始Ucs值，然后在高电流区域附近添加附加线路以减小Ucs值。

公开(公告)号：US08440521B2

公开(公告)日：2013-05-14

申请号：US13067788

申请日：2011-06-27

申请人： Naomi Fukumaki ,  Eiji Hasegawa ,  Toshihiro Iizuka ,  Ichiro Yamamoto

发明人： Naomi Fukumaki ,  Eiji Hasegawa ,  Toshihiro Iizuka ,  Ichiro Yamamoto

IPC分类号： H01L21/3105

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.

摘要翻译： 制造具有p型场效应晶体管和n型场效应晶体管的半导体器件的方法包括以下步骤：按照所述顺序在衬底上形成界面绝缘层和高电容率层; 在高电介质层上形成牺牲层的图案; 在形成有牺牲层的第一区域和形成牺牲层的第二区域的高介电常数层上形成含有金属元素的含金属膜; 通过进行热处理，将金属元素引入第二区域中的界面绝缘层与高电容率层之间的界面; 并且通过湿法蚀刻去除牺牲层，其中在去除步骤中，牺牲层比高介电常数层容易蚀刻。 由此，能够获得可靠性优异的半导体装置。

公开(公告)号：US08132572B2

公开(公告)日：2012-03-13

申请号：US12063357

申请日：2007-07-25

申请人： Hideyuki Kawabata ,  Koji Okamoto ,  Takashi Hoshina ,  Ryuhei Nagata ,  Yasuaki Nakatani ,  Terumi Shibano ,  Tomoaki Takada ,  Ryouji Kitamura ,  Toshiki Yajima ,  Daisuke Mouri ,  Kazuya Yamanaka ,  Ichiro Yamamoto ,  Shinji Katsura

发明人： Hideyuki Kawabata ,  Koji Okamoto ,  Takashi Hoshina ,  Ryuhei Nagata ,  Yasuaki Nakatani ,  Terumi Shibano ,  Tomoaki Takada ,  Ryouji Kitamura ,  Toshiki Yajima ,  Daisuke Mouri ,  Kazuya Yamanaka ,  Ichiro Yamamoto ,  Shinji Katsura

IPC分类号： A45D6/06

CPC分类号： A45D7/06 ,  A45D44/02

摘要： A permanent wave treatment apparatus comprises: a housing 3; a blower 1 which is installed within the housing to suck air and blow air; a steam separator 2 which is provided on the blower to remove water content from air sucked by suction force of the blower; an outlet hole formed in the housing through which air is spouted from the blower; hoods F mounted on the housing such that they are capable of being opened/closed freely; a plurality of rods R on which the hair of an object person is to be wound and in which air vent holes are formed; tubes 4 connected to the rods so as to keep the interior of the rods in a negative pressure by the suction force of the blower; and extraction member 5 which holds a plurality of the tubes such that they are capable of being extracted freely.

摘要翻译： 永久波处理装置包括：壳体3; 鼓风机1，其安装在壳体内以吸入空气并吹送空气; 蒸汽分离器2，其设置在鼓风机上，以通过鼓风机的吸力吸入的空气去除水分; 出口孔，形成在壳体中，空气从鼓风机喷出; 罩F安装在壳体上，使得它们能够自由地打开/关闭; 多个杆R，其上要形成有人的头发，其中形成有通气孔; 管4连接到杆上，以通过鼓风机的吸力将棒的内部保持在负压; 以及提取构件5，其保持多个管，使得它们能够自由地提取。

公开(公告)号：US20110088372A1

公开(公告)日：2011-04-21

申请号：US12906385

申请日：2010-10-18

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： F01N11/00 ,  F01N3/10 ,  F01N9/00

CPC分类号： B01D53/9431 ,  B01D53/9495 ,  F01N3/2026 ,  F01N3/208 ,  F01N2560/026 ,  F01N2610/02 ,  F01N2900/1402 ,  F01N2900/1602 ,  F01N2900/1622 ,  Y02T10/24 ,  Y02T10/26

摘要： An exhaust gas purification apparatus for an internal combustion engine includes an exhaust passage through which exhaust gas flows, a selective catalytic reduction (SCR) catalyst provided in the exhaust passage, a urea water supply device and a control unit for controlling amount of urea water to be supplied into the exhaust passage upstream of the SCR catalyst at predetermined intervals. The control unit further estimates amount of ammonia converted from adsorbed deposit which is converted from the urea water and adsorbed on the SCR catalyst during the predetermined interval based on a physical quantity of the internal combustion engine or the exhaust gas purification apparatus, and determines amount of urea water to be supplied into the exhaust passage based on the estimated amount of ammonia converted from the adsorbed deposit on the SCR catalyst.

摘要翻译： 用于内燃机的废气净化装置包括废气流过的排气通道，设置在排气通道中的选择性催化还原（SCR）催化剂，尿素供水装置和用于控制尿素水量的控制单元 以预定的间隔供给到SCR催化剂上游的排气通路。 控制单元进一步基于内燃机或排气净化装置的物理量，估计在预定间隔内从尿素水转化并吸附在SCR催化剂上的吸附沉积物转化的氨的量， 基于从SCR催化剂上的吸附沉积物转化的氨的估计量，将供给到排气通道中的尿素水。

公开(公告)号：US07307303B2

公开(公告)日：2007-12-11

申请号：US11120995

申请日：2005-05-04

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L28/40 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31641 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10852

摘要： A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1-X)OY (0.05≦x≦0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM (Metal Insulator Metal) structure, dielectric breakdown of a capacitor insulating film while a relative dielectric constant of a metal oxide film used as the capacitor insulating film is kept high.

摘要翻译： 提供了一种半导体器件，其具有由锆合金制成的电容器绝缘膜，其是通过具有包含无定形氧化铝并且其组成为Al x Zr（1- （0.05 <= x <= 0.3），因此能够在形成MIM（金属绝缘体金属）结构的电容器的过程中防止介电击穿 电容绝缘膜，而用作电容器绝缘膜的金属氧化物膜的相对介电常数保持较高。

公开(公告)号：US20070161201A1

公开(公告)日：2007-07-12

申请号：US11531610

申请日：2006-09-13

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31641 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10852

摘要： A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1−X)OY (0.05≦X≦0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM (Metal Insulator Metal) structure, dielectric breakdown of a capacitor insulating film while a relative dielectric constant of a metal oxide film used as the capacitor insulating film is kept high.

摘要翻译： 提供了一种半导体器件，其具有由锆合金制成的电容器绝缘膜，其是通过具有包含无定形氧化铝并且其组成为Al x Zr（1- （0.05 <= X <= 0.3），因此在形成MIM（金属绝缘体金属）结构的电容器的工艺中能够防止介电击穿 电容绝缘膜，而用作电容器绝缘膜的金属氧化物膜的相对介电常数保持较高。

公开(公告)号：US07033918B2

公开(公告)日：2006-04-25

申请号：US10749915

申请日：2003-12-31

申请人： Ichiro Yamamoto ,  Naohiko Kimizuka

发明人： Ichiro Yamamoto ,  Naohiko Kimizuka

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/2807

摘要： In a semiconductor device including at least one p-channel type MOS transistor, a silicon dioxide layer is formed on a silicon substrate, and a gate electrode is formed on the silicon dioxide layer. The gate electrode silicon has a three-layered structure including a silicon-seed layer formed on the silicon dioxide layer, a silicon/germanium layer formed on the silicon-seed layer, and a polycrystalline silicon layer on the silicon/germanium layer. An average grain size of polycrystalline silicon in the polycrystalline silicon layer is at most 100 nm, and p-type impurities are substantially uniformly distributed in the gate electrode along a height thereof, and the germanium atoms are diffused from the silicon/germanium layer into the silicon-seed layer at high density.

摘要翻译： 在包括至少一个p沟道型MOS晶体管的半导体器件中，在硅衬底上形成二氧化硅层，并且在二氧化硅层上形成栅电极。 栅电极硅具有三层结构，其包括在二氧化硅层上形成的硅 - 籽晶层，在硅 - 籽晶层上形成的硅/锗层和硅/锗层上的多晶硅层。 多晶硅层的多晶硅的平均晶粒尺寸为100nm以下，p型杂质沿栅极电极的高度大致均匀分布，锗原子从硅/锗层扩散到 硅籽晶层。

公开(公告)号：US06969876B2

公开(公告)日：2005-11-29

申请号：US11057742

申请日：2005-02-14

申请人： Ichiro Yamamoto ,  Naohiko Kimizuka

发明人： Ichiro Yamamoto ,  Naohiko Kimizuka

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/2807

摘要： In a semiconductor device including at least one p-channel type MOS transistor, a silicon dioxide layer is formed on a silicon substrate, and a gate electrode is formed on the silicon dioxide layer. The gate electrode silicon has a three-layered structure including a silicon-seed layer formed on the silicon dioxide layer, a silicon/germanium layer formed on the silicon-seed layer, and a polycrystalline silicon layer on the silicon/germanium layer. An average grain size of polycrystalline silicon in the polycrystalline silicon layer is at most 100 nm, and p-type impurities are substantially uniformly distributed in the gate electrode along a height thereof, and the germanium atoms are diffused from the silicon/germanium layer into the silicon-seed layer at high density.

摘要翻译： 在包括至少一个p沟道型MOS晶体管的半导体器件中，在硅衬底上形成二氧化硅层，并且在二氧化硅层上形成栅电极。 栅电极硅具有三层结构，其包括在二氧化硅层上形成的硅 - 籽晶层，在硅 - 籽晶层上形成的硅/锗层和硅/锗层上的多晶硅层。 多晶硅层的多晶硅的平均晶粒尺寸为100nm以下，p型杂质沿栅极电极的高度大致均匀分布，锗原子从硅/锗层扩散到 硅籽晶层。

公开(公告)号：US06956046B2

公开(公告)日：2005-10-18

申请号：US10478845

申请日：2002-05-17

申请人： Ichiro Yamamoto ,  Kazuyuki Matsuura ,  Kazuhiro Suzuki ,  Kazuo Kato ,  Yasushige Akada ,  Hidenori Mochizuki ,  Akihito Shimoi

发明人： Ichiro Yamamoto ,  Kazuyuki Matsuura ,  Kazuhiro Suzuki ,  Kazuo Kato ,  Yasushige Akada ,  Hidenori Mochizuki ,  Akihito Shimoi

IPC分类号： A61P29/00 ,  C07D211/48 ,  C07D401/12 ,  A61K31/44 ,  A61K31/4412

CPC分类号： C07D401/12 ,  C07D211/48

摘要： A compound represented by the following Formula (I): (wherein A represents oxygen atom or —NR3— (R3 represents hydrogen atom or lower alkyl group); R1 represents nitro group, lower alkoxycarbonyl group, carbamoyl group unsubstituted or mono- or di-substituted by lower alkyl group, unprotected or protected hydroxyl group, unprotected or protected carboxyl group, lower alkyl group substituted by unprotected or protected hydroxyl group, or tetrazolyl group; and R2 represents hydrogen atom, cyano group or lower alkylsulfonyl group, provided that when A is —NR3—, it is excluded that R1 represents unprotected or protected hydroxyl group or lower alkyl group substituted by unprotected or protected hydroxyl group) or its salt, and method for producing the compound, and a pharmaceutical composition containing the compound as active ingredient.

摘要翻译： 由下式（I）表示的化合物：其中A表示氧原子或-NR 3 - （R 3表示氢原子或低级烷基） SUP> 1表示硝基，低级烷氧基羰基，未取代的或被低级烷基单取代或未被保护或被保护的羟基，未被保护或保护的羧基，未被保护或被保护的羟基取代的低级烷基的氨基甲酰基 羟基或四唑基; R 2表示氢原子，氰基或低级烷基磺酰基，条件是当A是-NR 3 - 时，排除R 代表未被保护或保护的羟基或被未保护或被保护的羟基取代的低级烷基）或其盐，以及制备该化合物的方法，以及含有该化合物作为活性成分的药物组合物。