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    Method for fabricating a CMOS device
    1.
    发明授权
    Method for fabricating a CMOS device 失效
    CMOS器件制造方法

    公开(公告)号：US5750424A

    公开(公告)日：1998-05-12

    申请号：US764662

    申请日：1996-12-10

    Applicant: Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    Inventor： Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    IPC: H01L21/762 ,  H01L21/8238

    CPC classification number: H01L21/823864 ,  H01L21/76202 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823892

    Abstract: A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.

    Abstract translation: 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。

    Method for fabricating a CMOS device
    2.
    发明授权
    Method for fabricating a CMOS device 失效
    CMOS器件制造方法

    公开(公告)号：US5654213A

    公开(公告)日：1997-08-05

    申请号：US538533

    申请日：1995-10-03

    Applicant: Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    Inventor： Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/265

    CPC classification number: H01L21/823864 ,  H01L21/76202 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823892

    Abstract: A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.

    Abstract translation: 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。

    Nonvolatile memory cell structure for integration with semiconductor logic devices and method of using same
    4.
    发明授权
    Nonvolatile memory cell structure for integration with semiconductor logic devices and method of using same 失效
    用于与半导体逻辑器件集成的非易失性存储单元结构及其使用方法

    公开(公告)号：US06215701B1

    公开(公告)日：2001-04-10

    申请号：US09218026

    申请日：1998-12-22

    Applicant: Chingchi Yao ,  Chung-Jen Chien

    Inventor： Chingchi Yao ,  Chung-Jen Chien

    IPC: G11C1600

    CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

    Abstract: A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.

    Abstract translation: 非易失性存储单元包括第一和第二MOS晶体管，例如CMOS单元中的PMOS晶体管和NMOS晶体管。 两个晶体管之一提供用于存储数据的浮动栅极，而另一个晶体管设置有用于选择存储器单元的控制栅极，并且与用于读取存储在单元中的数据的位线连接。 非易失性存储单元可以使用形成在门阵列中的PMOS和NMOS晶体管单元集成到诸如CMOS门阵列的逻辑器件中。 在这种情况下，非易失性存储单元可以用用于产生逻辑器件的标准工艺制成逻辑器件。

    Dynamic random access memory cell suitable for integration with semiconductor logic devices
    6.
    发明授权
    Dynamic random access memory cell suitable for integration with semiconductor logic devices 失效
    适合与半导体逻辑器件集成的动态随机存取存储器

    公开(公告)号：US6097048A

    公开(公告)日：2000-08-01

    申请号：US218303

    申请日：1998-12-22

    Applicant: Chingchi Yao ,  Chung-Jen Chien ,  Thomas Chao

    Inventor： Chingchi Yao ,  Chung-Jen Chien ,  Thomas Chao

    IPC: H01L27/06 ,  H01L27/108

    CPC classification number: H01L27/0629 ,  H01L27/108 ,  H01L27/10897

    Abstract: A dynamic random access memory (DRAM) cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors functions as a switch transistor while the other transistor is configured as a storage capacitor. The DRAM cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the DRAM cell may be fabricated in a logic device with the standard processes used to produce the logic device.

    Abstract translation: 动态随机存取存储器（DRAM）单元包括第一和第二MOS晶体管，例如CMOS单元中的PMOS晶体管和NMOS晶体管。 两个晶体管中的一个用作开关晶体管，而另一个晶体管被配置为存储电容器。 可以使用形成在门阵列中的PMOS和NMOS晶体管单元将DRAM单元集成到诸如CMOS门阵列的逻辑器件中。 在这种情况下，可以使用用于产生逻辑器件的标准工艺在逻辑器件中制造DRAM单元。

    Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow
    7.
    发明授权
    Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow 失效
    制造完全集成在CMOS工艺流程中的BiCMOS集成电路的方法

    公开(公告)号：US5888861A

    公开(公告)日：1999-03-30

    申请号：US870474

    申请日：1997-06-06

    Applicant: Chung-Jen Chien ,  Jeong Y. Choi ,  Chuen-Der Lien

    Inventor： Chung-Jen Chien ,  Jeong Y. Choi ,  Chuen-Der Lien

    IPC: H01L21/8249 ,  H01L21/8238

    CPC classification number: H01L21/8249

    Abstract: A process for manufacturing a BiCMOS integrated circuit is implemented by adapting the masking and doping steps used in forming CMOS devices. Thus simultaneous formation of both CMOS and bipolar device structures eliminates the need for any additional masking or process steps to form bipolar device structures. Collector regions 20 of NPN transistors are formed simultaneously with N-wells 18. Collector regions of PNP transistors, if required, are formed simultaneously with P-wells 16. Base regions 24 of the bipolar transistors are formed using threshold voltage implant steps and/or lightly doped drain implant steps of PMOS transistors. Emitter regions 59 are formed, when using a single polysilicon CMOS process, simultaneously with the CMOS gates 72, 74. When employing a double polysilicon CMOS process, the emitter regions 59 are formed concurrently with the second polysilicon layer interconnect structure and/or source/drain regions 50,52 of NMOS transistors. For single polysilicon CMOS process, the buried layer regions 66 are formed during buried contact formation.

    Abstract translation: BiCMOS集成电路的制造工艺通过适应用于形成CMOS器件的掩模和掺杂步骤来实现。 因此同时形成CMOS和双极器件结构消除了对形成双极器件结构的任何附加掩模或工艺步骤的需要。 NPN晶体管的集电极区域20与N阱18同时形成。如果需要，PNP晶体管的集电极区域与P阱16同时形成。双极晶体管的基极区域24使用阈值电压注入步骤和/或 PMOS晶体管的轻掺杂漏极注入步骤。 当使用单个多晶硅CMOS工艺时，发射极区59与CMOS栅极72,74同时形成。当采用双重多晶硅CMOS工艺时，发射极区59与第二多晶硅层互连结构和/或源/ NMOS晶体管的漏极区域50,52。 对于单多晶硅CMOS工艺，在掩埋接触形成期间形成掩埋层区域66。

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