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    METHOD AND APPARATUS FOR DEBUGGING AN ELECTRONIC SYSTEM DESIGN (ESD) PROTOTYPE
    1.
    发明申请
    METHOD AND APPARATUS FOR DEBUGGING AN ELECTRONIC SYSTEM DESIGN (ESD) PROTOTYPE 审中-公开
    用于调试电子系统设计（ESD）原型的方法和装置

    公开(公告)号：US20100100860A1

    公开(公告)日：2010-04-22

    申请号：US12255606

    申请日：2008-10-21

    申请人： Chioumin M. Chang ,  Thomas B. Huang ,  Huan-Chih Tsai

    发明人： Chioumin M. Chang ,  Thomas B. Huang ,  Huan-Chih Tsai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027

    摘要： Using a vector-based emulation technique, a hardware-based prototyping system reduces time-consuming recompilation and reduces the iteration time for a verification run. The vector-based emulation technique takes advantage of information derived from user-defined probe points, automatically generated probe points and low-latency snapshots. Using a bounded-cycle simulation technique, the hardware-based prototyping system can provide complete or partial simulation traces covering interested signals and can efficiently evaluates assertions. A user is therefore able to debug in a real system test and to identify causes of fault conditions interactively under a controlled vector debugging environment.

    摘要翻译： 使用基于向量的仿真技术，基于硬件的原型系统可以减少耗时的重新编译，并减少验证运行的迭代时间。 基于矢量的仿真技术利用从用户定义的探测点，自动生成的探测点和低延迟快照得到的信息。 使用有界循环模拟技术，基于硬件的原型系统可以提供涵盖感兴趣信号的完整或部分模拟轨迹，并可以有效地评估断言。 因此，用户能够在真实的系统测试中进行调试，并在受控的向量调试环境下交互地识别故障条件的原因。

    Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution
    2.
    发明申请
    Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution 审中-公开
    使用矢量替换的矢量仿真验证逻辑电路的方法和装置

    公开(公告)号：US20100305933A1

    公开(公告)日：2010-12-02

    申请号：US12476012

    申请日：2009-06-01

    申请人： Chioumin M. Chang ,  Thomas B. Huang ,  Huan-Chih Tsai ,  Ting-Mao Chang

    发明人： Chioumin M. Chang ,  Thomas B. Huang ,  Huan-Chih Tsai ,  Ting-Mao Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027

    摘要： A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing emulation vectors for use in a vector emulation of the logic circuit in the prototyping system; (c) setting one or more vector substitution points; (d) preparing one or more packet vectors at each vector substitution point for replacing emulation vectors in the vector emulation; (e) performing the vector emulation using the emulation vectors until one of the vector substitution points is reached; and (f) substituting packet vectors for the corresponding emulation vectors at vector substitution point and continuing the vector emulation.

    摘要翻译： 用于验证原型系统中的逻辑电路的方法包括（a）配置原型系统的可编程逻辑电路以实现逻辑电路并实现用于访问逻辑电路的内部节点的探针电路; （b）准备用于原型系统逻辑电路的矢量仿真中的仿真矢量; （c）设置一个或多个向量替换点; （d）在每个向量替换点处准备一个或多个分组向量以替换所述向量仿真中的仿真向量; （e）使用仿真矢量执行矢量仿真，直到达到矢量替代点之一; 和（f）在矢量替换点处将分组向量替换为对应的仿真矢量并继续矢量仿真。

    SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING
    3.
    发明申请
    SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING 审中-公开
    用于原型调试的可扩展系统调试器

    公开(公告)号：US20120005547A1

    公开(公告)日：2012-01-05

    申请号：US12827917

    申请日：2010-06-30

    申请人： Chioumin M. Chang ,  Thomas B. Huang ,  Huan-Chih Tsai ,  Ting-Mao Chang

    发明人： Chioumin M. Chang ,  Thomas B. Huang ,  Huan-Chih Tsai ,  Ting-Mao Chang

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G06F11/261

    摘要： A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more programmable embedded debug circuits each receiving a first group of selected signals from the logic circuit under verification and providing control signals for (1) selecting a portion of the first group of selected signals, or (2) affecting the values of a second group of selected signals in the logic circuit under verification based on a portion of the first group of selected signals satisfying a predetermined triggering condition, wherein the programmable embedded debug circuits each including a built-in memory for storing signal vectors, the programmable embedded debug circuits each being configured according to a trigger specification defining one or more trigger states and triggering conditions; and (iii) a local debugging controller that controls programmable embedded debug circuits and transfers signal vectors between the built-in memories of the programmable embedded debug circuits and the vector processor interface bus; and (c) a vector processor which controls transferring of signal vectors between the host processor and the vector processor interface bus.

    摘要翻译： 由主处理器通过主机总线控制的原型调试系统包括：（a）向量处理器接口总线; （b）一个或多个可编程逻辑电路，其中至少一个被提供用于实现：（i）正在验证的逻辑电路; （ii）一个或多个可编程嵌入式调试电路，每个接收来自所述逻辑电路的第一组选定信号，并且提供用于（1）选择所述第一组选定信号的一部分的控制信号，或（2）影响所述值 基于满足预定触发条件的所述第一组选择信号的一部分，所述逻辑电路中的所选逻辑电路中的第二组选择信号，其中所述可编程嵌入式调试电路各自包括用于存储信号向量的内置存储器，所述可编程 嵌入式调试电路各自根据定义一个或多个触发状态和触发条件的触发规范进行配置; 和（iii）本地调试控制器，其控制可编程嵌入式调试电路并在可编程嵌入式调试电路的内置存储器和矢量处理器接口总线之间传送信号矢量; 以及（c）矢量处理器，其控制主处理器和矢量处理器接口总线之间的信号矢量的传送。

    VIRTUAL INTERCONNECTION METHOD AND APPARATUS
    4.
    发明申请
    VIRTUAL INTERCONNECTION METHOD AND APPARATUS 审中-公开
    虚拟互连方法和设备

    公开(公告)号：US20110289469A1

    公开(公告)日：2011-11-24

    申请号：US12785283

    申请日：2010-05-21

    申请人： Thomas B. Huang ,  Chioumin M. Chang ,  Huan-Chih Tsai ,  Ting-Mao Chang

    发明人： Thomas B. Huang ,  Chioumin M. Chang ,  Huan-Chih Tsai ,  Ting-Mao Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027

    摘要： A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuits each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions. The prototyping system is associated with a method for prototyping an electronic design, which includes (i) compiling an electronic design into (a) multiple partitions, each partition being compiled for implementation in a programmable logic circuit (e.g., a field programmable gate array integrated circuit), and (b) multiple connections that connect signals between the partition; and (ii) compiling into each programmable logic circuit an interface circuit module for managing the connections using a virtual interconnection technique.

    摘要翻译： 原型系统包括（i）具有用于与主处理器通信的接口的矢量处理器和用于调度矢量的第二接口（例如，矢量处理器总线）; （ii）多个可编程逻辑电路，每个可编程逻辑电路都耦合到第二接口以接收发送的矢量; （iii）编译器，用于（a）将电子电路划分成多个分区，将每个分区分配给可编程逻辑电路之一，（b）提供多个连接，每个连接提供用于在分区之间连接信号，（c） 可编程逻辑电路，使用虚拟互连技术管理分区之间的连接的接口电路模块，以及（d）分配物理互连资源，例如可编程逻辑电路的引脚和物理线。 首先进一步分配分区之间的至少一个虚拟互连（辅助I / O），以实现分区之间的连接。 原型系统与用于原型设计电子设计的方法相关联，其包括（i）将电子设计编译成（a）多个分区，每个分区被编译用于在可编程逻辑电路中实现（例如，集成的现场可编程门阵列 电路），和（b）连接分区之间的信号的多个连接; 和（ii）将每个可编程逻辑电路编译成用于使用虚拟互连技术来管理连接的接口电路模块。

    Method and system for equivalence checking of a low power design
    5.
    发明申请
    Method and system for equivalence checking of a low power design 有权
    低功耗设计的等效性检查方法和系统

    公开(公告)号：US20080127014A1

    公开(公告)日：2008-05-29

    申请号：US11586879

    申请日：2006-10-25

    申请人： Manish Pandey ,  Rajat Arora ,  Chih-Chang Lin ,  Huan-Chih Tsai ,  Bharat Chandramouli ,  Kei-Yong Khoo

    发明人： Manish Pandey ,  Rajat Arora ,  Chih-Chang Lin ,  Huan-Chih Tsai ,  Bharat Chandramouli ,  Kei-Yong Khoo

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.

    摘要翻译： 公开了低功率设计的等效性检验方法和系统。 该方法包括接收电路的寄存器传送级（RTL）网表表示，接收用于描述电路的功率需求的功率指定文件，创建用于表示使用RTL网表的电路的设计实现的低功率门网表，以及 电源规范文件，创建用于表示使用RTL网表和电源规格文件的电路的设计规范的参考低功率RTL网表，以及执行低功率门网表和参考低功率RTL网表之间的等价检查。 该方法还包括将电力规范文件中描述的低功率信息注释到参考低功率RTL网表中，以及在参考低功率RTL网表中创建低功率逻辑。

    Method and mechanism for implementing electronic designs having power information specifications background
    6.
    发明授权
    Method and mechanism for implementing electronic designs having power information specifications background 有权
    实现具有电力信息规格背景的电子设计的方法和机制

    公开(公告)号：US08516422B1

    公开(公告)日：2013-08-20

    申请号：US12815239

    申请日：2010-06-14

    申请人： Qi Wang ,  Ankur Gupta ,  Pinhong Chen ,  Christina Chu ,  Manish Pandey ,  Huan-Chih Tsai ,  Sandeep Bhatia ,  Yonghao Chen ,  Steven Sharp ,  Vivek Chickermane ,  Patrick Gallagher

    发明人： Qi Wang ,  Ankur Gupta ,  Pinhong Chen ,  Christina Chu ,  Manish Pandey ,  Huan-Chih Tsai ,  Sandeep Bhatia ,  Yonghao Chen ,  Steven Sharp ,  Vivek Chickermane ,  Patrick Gallagher

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5081 ,  G06F2217/78

    摘要： A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

    摘要翻译： 一种用于实现用于IC的功率相关信息的单个文件格式的方法，包括：在非暂时性计算机可读存储设备中的至少一个设计文件中提供电路设计; 在与所述至少一个设计文件分离的并且指定所述电路设计中的多个电力域的所述计算机可读存储设备中的文件中提供电力相关设计信息，每个电力域包括来自所述电路内的一个或多个设计对象实例 并且指定多个功率模式，每个功率模式对应于多个指定功率域的开/关状态的不同组合，并且指定相对于相应功率域的隔离行为; 并且使用计算机将功率控制电路添加到实现功率规范信息中指定的功率域和功率模式以及隔离行为的电路设计。

    Method and system for verifying power specifications of a low power design
    9.
    发明申请
    Method and system for verifying power specifications of a low power design 有权
    用于验证低功率设计功率规格的方法和系统

    公开(公告)号：US20080127015A1

    公开(公告)日：2008-05-29

    申请号：US11590076

    申请日：2006-10-30

    申请人： Bharat Chandramouli ,  Huan-Chih Tsai ,  Manish Pandey ,  Chih-Chang Lin ,  Madan M. Das

    发明人： Bharat Chandramouli ,  Huan-Chih Tsai ,  Manish Pandey ,  Chih-Chang Lin ,  Madan M. Das

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F2217/78

    摘要： Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.

    摘要翻译： 公开了用于验证低功率设计的功率规格的方法和系统。 该方法包括接收低功率设计的寄存器传送级（RTL）网表表示，接收用于描述低功率设计的功率需求的功率规格文件，并根据低功率设计的RTL网表表示验证功率规格文件 电源设计。 该方法还包括验证低功率设计的功率要求的完整性，兼容性和一致性。