公开(公告)号：US20110159443A1

公开(公告)日：2011-06-30

申请号：US13041696

申请日：2011-03-07

申请人： Choong-Ryul Ryou ,  Hee-Sung Kang

发明人： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC分类号： G03F7/20

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

摘要： A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

摘要翻译： 描述了在半导体器件中形成图案的方法。 提供分为单元和外围区域的基板，在基板上形成对象层。 沿着第一方向在单元区域中的对象层上形成缓冲图案。 沿着单元区域中的缓冲图案的侧壁形成间隔物，并且在外围区域中的目标层上残留有硬掩模层。 去除缓冲层，并且沿着与第一方向不同的第二方向分离间隔物，从而形成单元硬掩模图案。 在外围区域形成外围硬掩模图案。 使用基板中的单元和外围硬掩模图案形成微小图案。 因此，由于光刻工艺引起的线宽变化或边缘线粗糙度被最小化。

公开(公告)号：US20060194436A1

公开(公告)日：2006-08-31

申请号：US11353348

申请日：2006-02-14

申请人： Myoung-Hwan Oh ,  Hee-Sung Kang ,  Choong-Ryul Ryou

发明人： Myoung-Hwan Oh ,  Hee-Sung Kang ,  Choong-Ryul Ryou

IPC分类号： H01L21/302

CPC分类号： H01L27/08 ,  H01L29/8605

摘要： In a semiconductor device including a resistor and a method of fabricating the same, the semiconductor device includes an isolation insulating layer disposed in a semiconductor substrate to define at least two active regions spaced from each other. A well resistor pattern is disposed below the isolation insulating layer to connect the active regions. An upper resistor pattern is disposed on the isolation insulating layer between the active regions. A resistor connector electrically connects a selected one of the active regions with the upper resistor pattern so that the well resistor pattern and the upper resistor pattern are connected in series.

摘要翻译： 在包括电阻器的半导体器件及其制造方法中，半导体器件包括设置在半导体衬底中以限定彼此间隔开的至少两个有源区的隔离绝缘层。 良好的电阻器图案设置在隔离绝缘层下方以连接有源区。 上电阻图案设置在有源区之间的隔离绝缘层上。 电阻器连接器将所选择的一个有源区域与上部电阻器图案电连接，使得阱电阻器图案和上部电阻器图案串联连接。

公开(公告)号：US07045429B2

公开(公告)日：2006-05-16

申请号：US11049533

申请日：2005-02-02

申请人： Jin-Hua Liu ,  Hee-Sung Kang ,  Choong-Ryul Ryou

发明人： Jin-Hua Liu ,  Hee-Sung Kang ,  Choong-Ryul Ryou

IPC分类号： H01L21/336

CPC分类号： H01L29/66484 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

摘要： In a method of manufacturing a semiconductor device, a device including gate electrodes and asymmetric source and drain regions is formed by employing a semiconductor layer structure. The short channel effect is prevented in the resulting device even though the gate electrodes are of a dimension on the order of nanometers. Additionally, the gate electrodes and asymmetric source and drain regions of the semiconductor device may be precisely formed to have dimensions on the nanometer scale because a semiconductor layer structure is used in the process for manufacturing the semiconductor device.

摘要翻译： 在制造半导体器件的方法中，通过采用半导体层结构形成包括栅电极和不对称源极和漏极区的器件。 即使栅电极的尺寸为纳米级，在所得到的器件中也防止了短沟道效应。 此外，半导体器件的栅极电极和非对称源极和漏极区域可以被精确地形成为具有纳米尺度的尺寸，因为在用于制造半导体器件的工艺中使用半导体层结构。

公开(公告)号：US20080261156A1

公开(公告)日：2008-10-23

申请号：US12146092

申请日：2008-06-25

申请人： Choong-Ryul Ryou ,  Hee-Sung Kang

发明人： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC分类号： G03F7/20

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

摘要： A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

摘要翻译： 描述了在半导体器件中形成图案的方法。 提供分为单元和外围区域的基板，在基板上形成对象层。 沿着第一方向在单元区域中的对象层上形成缓冲图案。 沿着单元区域中的缓冲图案的侧壁形成间隔物，并且在外围区域中的目标层上残留有硬掩模层。 去除缓冲层，并且沿着与第一方向不同的第二方向分离间隔物，从而形成单元硬掩模图案。 在外围区域形成外围硬掩模图案。 使用基板中的单元和外围硬掩模图案形成微小图案。 因此，由于光刻工艺引起的线宽变化或边缘线粗糙度被最小化。

公开(公告)号：US08409787B2

公开(公告)日：2013-04-02

申请号：US13041696

申请日：2011-03-07

申请人： Choong-Ryul Ryou ,  Hee-Sung Kang

发明人： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC分类号： H01L21/00 ,  H01L21/76

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

摘要： A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

公开(公告)号：US07914973B2

公开(公告)日：2011-03-29

申请号：US12146092

申请日：2008-06-25

申请人： Choong-Ryul Ryou ,  Hee-Sung Kang

发明人： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC分类号： H01L21/00 ,  H01L21/76

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

摘要： A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

摘要翻译： 描述了在半导体器件中形成图案的方法。 提供分为单元和外围区域的基板，在基板上形成对象层。 沿着第一方向在单元区域中的对象层上形成缓冲图案。 沿着单元区域中的缓冲图案的侧壁形成间隔物，并且在外围区域中的目标层上残留有硬掩模层。 去除缓冲层，并且沿着与第一方向不同的第二方向分离间隔物，从而形成单元硬掩模图案。 在外围区域形成外围硬掩模图案。 使用基板中的单元和外围硬掩模图案形成微小图案。 因此，由于光刻工艺引起的线宽变化或边缘线粗糙度被最小化。

公开(公告)号：US20060240636A1

公开(公告)日：2006-10-26

申请号：US11358454

申请日：2006-02-21

申请人： Hyuk-Ju Ryu ,  Heon-Jong Shin ,  Hee-Sung Kang ,  Choong-Ryul Ryou ,  Mu-Kyeng Jung ,  Kyung-Soo Kim

发明人： Hyuk-Ju Ryu ,  Heon-Jong Shin ,  Hee-Sung Kang ,  Choong-Ryul Ryou ,  Mu-Kyeng Jung ,  Kyung-Soo Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/76224 ,  H01L21/823878

摘要： In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.

摘要翻译： 在沟槽隔离方法中，制备具有N-MOS区和P-MOS区的半导体衬底。 在N-MOS区形成露出N-MOS场区的第一掩模图案，在P-MOS区形成露出P-MOS场区的第二掩模图案。 形成第一光致抗蚀剂图案以覆盖P-MOS区域并暴露N-MOS区域。 使用第一掩模图案和第一光致抗蚀剂图案作为离子注入掩模将第一杂质离子注入到N-MOS区域中，从而在N-MOS场区域中形成第一杂质层。 在这种情况下，第一杂质层的一部分形成为延伸到第一掩模图案的下方。 去除第一光致抗蚀剂图案。 使用第一和第二掩模图案作为蚀刻掩模蚀刻半导体衬底，从而在N-MOS场区和P-MOS场区中形成沟槽，同时，形成第一杂质图案的第一杂质图案保留在第一 掩模图案。 然后形成填充沟槽的沟槽隔离层。

公开(公告)号：US20050176207A1

公开(公告)日：2005-08-11

申请号：US11049533

申请日：2005-02-02

申请人： Jin-Hua Liu ,  Hee-Sung Kang ,  Choong-Ryul Ryou

发明人： Jin-Hua Liu ,  Hee-Sung Kang ,  Choong-Ryul Ryou

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66484 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

摘要： In a method of manufacturing a semiconductor device, a device including gate electrodes and asymmetric source and drain regions is formed by employing a semiconductor layer structure. The short channel effect is prevented in the resulting device even though the gate electrodes are of a dimension on the order of nanometers. Additionally, the gate electrodes and asymmetric source and drain regions of the semiconductor device may be precisely formed to have dimensions on the nanometer scale because a semiconductor layer structure is used in the process for manufacturing the semiconductor device.

摘要翻译： 在制造半导体器件的方法中，通过采用半导体层结构形成包括栅电极和不对称源极和漏极区的器件。 即使栅电极的尺寸为纳米级，在所得到的器件中也防止了短沟道效应。 此外，半导体器件的栅极电极和非对称源极和漏极区域可以被精确地形成为具有纳米尺度的尺寸，因为在用于制造半导体器件的工艺中使用半导体层结构。

公开(公告)号：US20050142497A1

公开(公告)日：2005-06-30

申请号：US11020825

申请日：2004-12-22

申请人： Choong-Ryul Ryou ,  Hee-Sung Kang

发明人： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC分类号： H01L21/027 ,  G03F7/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

摘要： A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

摘要翻译： 描述了在半导体器件中形成图案的方法。 提供分为单元和外围区域的基板，在基板上形成对象层。 沿着第一方向在单元区域中的对象层上形成缓冲图案。 沿着单元区域中的缓冲图案的侧壁形成间隔物，并且在外围区域中的目标层上残留有硬掩模层。 去除缓冲层，并且沿着与第一方向不同的第二方向分离间隔物，从而形成单元硬掩模图案。 在外围区域形成外围硬掩模图案。 使用基板中的单元和外围硬掩模图案形成微小图案。 因此，由于光刻工艺引起的线宽变化或边缘线粗糙度被最小化。

公开(公告)号：US20080032483A1

公开(公告)日：2008-02-07

申请号：US11973044

申请日：2007-10-05

申请人： Hyuk-Ju Ryu ,  Heon-Jong Shin ,  Hee-Sung Kang ,  Choong-Ryul Ryou ,  Mu-Kyeng Jung ,  Kyung-Soo Kim

发明人： Hyuk-Ju Ryu ,  Heon-Jong Shin ,  Hee-Sung Kang ,  Choong-Ryul Ryou ,  Mu-Kyeng Jung ,  Kyung-Soo Kim

IPC分类号： H01L21/78

CPC分类号： H01L21/76237 ,  H01L21/76224 ,  H01L21/823878

摘要： In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.

摘要翻译： 在沟槽隔离方法中，制备具有N-MOS区和P-MOS区的半导体衬底。 在N-MOS区形成露出N-MOS场区的第一掩模图案，在P-MOS区形成露出P-MOS场区的第二掩模图案。 形成第一光致抗蚀剂图案以覆盖P-MOS区并暴露N-MOS区。 使用第一掩模图案和第一光致抗蚀剂图案作为离子注入掩模将第一杂质离子注入到N-MOS区域中，从而在N-MOS场区域中形成第一杂质层。 在这种情况下，第一杂质层的一部分形成为延伸到第一掩模图案的下方。 去除第一光致抗蚀剂图案。 使用第一和第二掩模图案作为蚀刻掩模蚀刻半导体衬底，从而在N-MOS场区和P-MOS场区中形成沟槽，同时，形成第一杂质图案的第一杂质图案保留在第一 掩模图案。 然后形成填充沟槽的沟槽隔离层。