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    Method for preparing cerium carbonate powder using urea
    2.
    发明授权
    Method for preparing cerium carbonate powder using urea 有权
    使用尿素制备碳酸铈粉末的方法

    公开(公告)号：US08303918B2

    公开(公告)日：2012-11-06

    申请号：US12531452

    申请日：2008-03-14

    申请人： Myoung-Hwan Oh ,  Seung-Beom Cho ,  Jun-Seok Nho ,  Jong-Pil Kim ,  Jang-Yul Kim ,  Dong-Mok Shin

    发明人： Myoung-Hwan Oh ,  Seung-Beom Cho ,  Jun-Seok Nho ,  Jong-Pil Kim ,  Jang-Yul Kim ,  Dong-Mok Shin

    IPC分类号： C01F17/00 ,  C09K3/14

    CPC分类号： C01F17/005 ,  C01P2002/72

    摘要： In a method for preparing cerium carbonate powder by mixing a cerium precursor solution with a urea solution and carrying out a precipitation reaction, wherein the cerium carbonate powder has a hexagonal crystal structure, by using at least one type of organic solvent as a solvent for either or both the cerium precursor solution and the urea solution, and adjusting temperature of the precipitation reaction within a range of 120° C. to 300° C. Also, the method can yield cerium carbonate powder, cerium oxide powder from the cerium carbonate powder, and CMP slurry including the cerium oxide powder as an abrasive. In the method, urea as a precipitant can improve the uniformity of a reaction, and thus it is possible to easily and inexpensively obtain cerium carbonate powder with a hexagonal crystal structure without the danger by high-temperature high-pressure and the need for an expensive system in hydrothermal synthesis.

    摘要翻译： 在通过将铈前体溶液与尿素溶液混合并进行沉淀反应制备碳酸铈粉末的方法中，其中所述碳酸铈粉末具有六方晶系结构，通过使用至少一种有机溶剂作为溶剂用于任一种 或铈前体溶液和尿素溶液两者，并将沉淀反应的温度调节在120℃至300℃的范围内。此外，该方法可以从碳酸铈粉末中得到碳酸铈粉末，氧化铈粉末， 和包括氧化铈粉末作为研磨剂的CMP浆料。 在该方法中，作为沉淀剂的尿素可以提高反应的均匀性，因此可以容易且廉价地获得六方晶系结构的碳酸铈粉末，而不会受到高温高压的危险，并且需要昂贵的 水热合成系统。

    Method for preparing cerium oxide powder using organic solvent and CMP slurry comprising the same
    3.
    发明授权
    Method for preparing cerium oxide powder using organic solvent and CMP slurry comprising the same 有权
    使用有机溶剂制备氧化铈粉末的方法和包含该方法的CMP浆料

    公开(公告)号：US08173039B2

    公开(公告)日：2012-05-08

    申请号：US12312601

    申请日：2007-11-20

    申请人： Jun-Seok Nho ,  Myoung-Hwan Oh ,  Seung-Beom Cho ,  Jong-Pil Kim ,  Jang-Yul Kim

    发明人： Jun-Seok Nho ,  Myoung-Hwan Oh ,  Seung-Beom Cho ,  Jong-Pil Kim ,  Jang-Yul Kim

    IPC分类号： C09K13/00

    CPC分类号： C09G1/02 ,  B82Y30/00 ,  C01F17/0043 ,  C01P2002/72 ,  C01P2002/76 ,  C01P2004/03 ,  C01P2004/62 ,  C01P2004/64 ,  C01P2006/12 ,  C09K3/1409 ,  H01L21/31053 ,  Y10T428/2982

    摘要： Disclosed is a method for directly preparing cerium oxide powder in a solution phase by a) mixing a cerium precursor solution with a precipitant solution to cause a reaction; and b) performing oxidation treatment of the reacted solution, wherein at least one kind of pure organic solvent containing no water is used as a solvent for the cerium precursor solution as well as the precipitant solution to thereby prepare the cerium oxide powder, the particle size of which is adjusted to 50 nm to 3 μm. Cerium oxide powder obtained from the method and CMP slurry comprising the cerium oxide powder as a polishing agent are also disclosed. The method makes it possible to prepare cerium oxide powder with an average particle size of 50 nm or greater and high crystallinity, which is difficult to prepare by the conventional wet precipitation process, by using an organic solvent as a solvent in a wet precipitation process, and the so-prepared cerium oxide powder can be used as a polishing agent for CMP slurry even without being subjected to separate heat treatment.

    摘要翻译： 公开了一种通过以下步骤直接制备氧化铈粉末的方法：a）将铈前体溶液与沉淀剂溶液混合以引起反应; 和b）对反应溶液进行氧化处理，其中使用至少一种不含水的纯有机溶剂作为铈前体溶液的溶剂以及沉淀剂溶液，从而制备氧化铈粉末，其粒径 调整为50nm〜3μm。 还公开了由该方法获得的氧化铈粉末和包含氧化铈粉末作为抛光剂的CMP浆料。 该方法可以通过在湿沉淀法中使用有机溶剂作为溶剂来制备平均粒径为50nm以上的高结晶度的氧化铈粉末，这在常规的湿法沉淀法难以制备， 并且如此制备的氧化铈粉末即使不经过单独的热处理也可用作CMP浆料的抛光剂。

    Method for preparing cerium carbonate powder
    4.
    发明授权
    Method for preparing cerium carbonate powder 有权
    碳酸铈粉末的制备方法

    公开(公告)号：US07976810B2

    公开(公告)日：2011-07-12

    申请号：US12531450

    申请日：2008-03-14

    申请人： Myoung-Hwan Oh ,  Seung-Beom Cho ,  Jun-Seok Nho ,  Jong-Pil Kim ,  Jang-Yul Kim

    发明人： Myoung-Hwan Oh ,  Seung-Beom Cho ,  Jun-Seok Nho ,  Jong-Pil Kim ,  Jang-Yul Kim

    IPC分类号： C01B31/24

    CPC分类号： C01F17/0043 ,  C01F17/005 ,  C01P2002/72 ,  C01P2002/76 ,  C09K3/1409 ,  C09K3/1463

    摘要： In a method for preparing cerium carbonate powder by mixing a cerium precursor solution with a carbonate precursor solution and carrying out a precipitation reaction, wherein cerium carbonate is controlled to have an orthorhombic crystal structure, a hexagonal crystal structure or an orthorhombic/hexagonal mixed crystal structure, by using at least one type of organic solvent comprising at least two hydroxyl groups (OH) in molecular formula as a solvent for either or both the cerium precursor solution and the carbonate precursor solution, and varying a number of carbons or hydroxyl groups (OH) included in the molecular formula of the organic solvent. The method can easily and inexpensively obtain cerium carbonate powder with a desired crystal structure without the danger by high-temperature high-pressure and the need for an expensive system in hydrothermal synthesis.

    摘要翻译： 在通过将铈前体溶液与碳酸酯前体溶液混合并进行沉淀反应制备碳酸铈粉末的方法中，其中将碳酸铈控制为具有正交晶体结构，六方晶系结构或正交/六方晶系混合晶体结构 通过使用包含分子式中的至少两个羟基（OH）的至少一种类型的有机溶剂作为铈前体溶液和碳酸酯前体溶液中的任一种或两者的溶剂，并且改变多个碳或羟基（OH ）包括在有机溶剂的分子式中。 该方法可以容易且廉价地获得具有所需晶体结构的碳酸铈粉末，而没有高温高压的危险和需要昂贵的水热合成系统。

    Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same
    6.
    发明授权
    Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same 有权
    具有确保接触边缘的硅化物层的高度集成的半导体器件及其制造方法

    公开(公告)号：US07338874B2

    公开(公告)日：2008-03-04

    申请号：US11488239

    申请日：2006-07-18

    申请人： Myoung-hwan Oh ,  Young-gun Ko

    发明人： Myoung-hwan Oh ,  Young-gun Ko

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7835

    摘要： Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A silicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

    摘要翻译： 提供了一种具有硅化物层的高度集成的半导体器件，其可以确保接触边缘，以及制造高度集成的半导体器件的方法。 高度集成的半导体器件包括形成在半导体衬底上的栅电极。 源极区域和漏极区域形成在栅极电极的两侧的半导体衬底的预定上部中，使得源极区域和漏极区域中的每一个包括轻掺杂漏极（LDD）区域和重掺杂区域。 在栅电极，源极区和漏极区上形成硅化物层。 硅化物层具有足够的厚度以用作欧姆接触，并且形成在LDD区域和源极区域和漏极区域中的每一个的重掺杂区域上。

    Method of fabricating MOS transistor having fully silicided gate
    7.
    发明授权
    Method of fabricating MOS transistor having fully silicided gate 有权
    制造具有完全硅化栅的MOS晶体管的方法

    公开(公告)号：US07179714B2

    公开(公告)日：2007-02-20

    申请号：US11065242

    申请日：2005-02-24

    申请人： You-Jean Chang ,  Myoung-Hwan Oh ,  Hee-Sung Kang ,  Choong-Ryul Ryou

    发明人： You-Jean Chang ,  Myoung-Hwan Oh ,  Hee-Sung Kang ,  Choong-Ryul Ryou

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate pattern, which are sequentially stacked. Source/drain regions are formed by implanting impurity ions into an active region using the gate pattern and the gate spacers as ion implantation masks. Then, a protecting layer is formed on the semiconductor substrate having the gate pattern, and the protecting layer is planarized until the upper gate pattern is exposed. Then, by removing the exposed upper gate pattern and the insulating layer pattern, the lower gate pattern is exposed. Then, the protecting layer is selectively removed, thereby exposing the source/drain regions. The exposed lower gate pattern is fully converted to a gate silicide layer, and a silicide layer is concurrently formed on the surfaces of the source/drain regions.

    摘要翻译： 提供了一种制造具有完全硅化栅极的MOS晶体管的方法，包括在半导体衬底上形成栅极图案和栅极间隔物，该栅极图案包括下部栅极图案，绝缘层图案和上部栅格图案，其中 顺序堆叠。 通过使用栅极图案和栅极间隔物作为离子注入掩模将杂质离子注入有源区域来形成源极/漏极区域。 然后，在具有栅极图案的半导体衬底上形成保护层，并且将保护层平坦化直到上部栅极图案露出。 然后，通过去除暴露的上部栅极图案和绝缘层图案，露出下部栅极图案。 然后，选择性地去除保护层，从而使源极/漏极区域露出。 暴露的下栅极图案完全转换为栅极硅化物层，并且在源极/漏极区域的表面上同时形成硅化物层。

    Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same
    8.
    发明授权
    Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same 有权
    具有确保接触边缘的硅化物层的高度集成的半导体器件及其制造方法

    公开(公告)号：US07098514B2

    公开(公告)日：2006-08-29

    申请号：US10862996

    申请日：2004-06-08

    申请人： Myoung-hwan Oh ,  Young-gun Ko

    发明人： Myoung-hwan Oh ,  Young-gun Ko

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/62 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7835

    摘要： Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A suicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

    摘要翻译： 提供了一种具有硅化物层的高度集成的半导体器件，其可以确保接触边缘，以及制造高度集成的半导体器件的方法。 高度集成的半导体器件包括形成在半导体衬底上的栅电极。 源极区域和漏极区域形成在栅极电极的两侧的半导体衬底的预定上部中，使得源极区域和漏极区域中的每一个包括轻掺杂漏极（LDD）区域和重掺杂区域。 在栅极电极，源极区域和漏极区域上形成硅化物层。 硅化物层具有足够的厚度以用作欧姆接触，并且形成在LDD区域和源极区域和漏极区域中的每一个的重掺杂区域上。

    Method of fabricating MOS transistor having fully silicided gate
    9.
    发明申请
    Method of fabricating MOS transistor having fully silicided gate 有权
    制造具有完全硅化栅的MOS晶体管的方法

    公开(公告)号：US20050191833A1

    公开(公告)日：2005-09-01

    申请号：US11065242

    申请日：2005-02-24

    申请人： You-Jean Chang ,  Myoung-Hwan Oh ,  Hee-Sung Kang ,  Choong-Ryul Ryou

    发明人： You-Jean Chang ,  Myoung-Hwan Oh ,  Hee-Sung Kang ,  Choong-Ryul Ryou

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/4763

    CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate pattern, which are sequentially stacked. Source/drain regions are formed by implanting impurity ions into an active region using the gate pattern and the gate spacers as ion implantation masks. Then, a protecting layer is formed on the semiconductor substrate having the gate pattern, and the protecting layer is planarized until the upper gate pattern is exposed. Then, by removing the exposed upper gate pattern and the insulating layer pattern, the lower gate pattern is exposed. Then, the protecting layer is selectively removed, thereby exposing the source/drain regions. The exposed lower gate pattern is fully converted to a gate silicide layer, and a silicide layer is concurrently formed on the surfaces of the source/drain regions.

    摘要翻译： 提供了一种制造具有完全硅化栅极的MOS晶体管的方法，包括在半导体衬底上形成栅极图案和栅极间隔物，该栅极图案包括下部栅极图案，绝缘层图案和上部栅格图案，其中 顺序堆叠。 通过使用栅极图案和栅极间隔物作为离子注入掩模将杂质离子注入有源区域来形成源极/漏极区域。 然后，在具有栅极图案的半导体衬底上形成保护层，并且将保护层平坦化直到上部栅极图案露出。 然后，通过去除暴露的上部栅极图案和绝缘层图案，露出下部栅极图案。 然后，选择性地去除保护层，从而使源极/漏极区域露出。 暴露的下栅极图案完全转换为栅极硅化物层，并且在源极/漏极区域的表面上同时形成硅化物层。