公开(公告)号：US06972701B2

公开(公告)日：2005-12-06

申请号：US10950271

申请日：2004-09-24

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03M1/10 ,  H03M1/36 ,  H03M1/70 ,  H03M1/62 ,  H03M1/84 ,  H03M1/88

CPC classification number: H03M1/1019 ,  H03M1/361 ,  H03M1/70

Abstract: A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.

Abstract translation: 包括具有相关联的校准D / A转换器的一组比较器的A / D转换器结构中的AD / A转换器范围校准系统包括用于确定整个比较器组的偏移误差范围的装置（RCC）和装置（R-DAC） 用于将每个校准D / A转换器的动态范围调整到该偏移误差范围。

公开(公告)号：US06778110B2

公开(公告)日：2004-08-17

申请号：US10668000

申请日：2003-09-22

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03M110

CPC classification number: H03M7/165 ,  H03M1/1004 ,  H03M1/1061 ,  H03M1/167 ,  H03M1/36

Abstract: An A/D converter includes a calibration apparatus handling occurrences of thermometer code bubbles in an A/D sub-converter in at least one A/D converter stage. The calibration apparatus includes means (30) for detecting two A/D sub-converter comparators causing a bubble, means (32, 34, 36) for increasing the threshold of the bubble causing comparator having the lowest threshold by a first predetermined voltage and means (32, 34, 36) for decreasing the threshold of the bubble causing comparator having the highest threshold by a second predetermined voltage.

Abstract translation: A / D转换器包括校准装置，其处理在至少一个A / D转换器级中的A / D子转换器中出现的温度计代码气泡。 校准装置包括用于检测引起气泡的两个A / D子转换器比较器的装置（30），用于将具有最低阈值的气泡引起的比较器的阈值增加第一预定电压的装置（32,34,36） （32,34,36），用于将具有最高阈值的气泡引起的比较器的阈值减小第二预定电压。

公开(公告)号：US20160278382A1

公开(公告)日：2016-09-29

申请号：US14364321

申请日：2012-12-06

Applicant: Chuanxin SUN ,  Christer JANSSON

Inventor： Chuanxin Sun ,  Christer Jansson

IPC: A01N43/90 ,  C12N15/82

CPC classification number: A01N43/90 ,  A01N57/16 ,  A01N63/02 ,  A01N65/00 ,  C12N15/821 ,  C12N15/8218

Abstract: The invention relates to a method of producing transgenic plant material by transforming a plant with a vector comprising an essential gene having mutations at two sites at least. The method is exemplified with EPSPS as the essential gene. The method makes it possible to use an antisense molecule directed to the native form of said gene for selection of transformed plants. The application relates further to a plant obtainable by the method, a binary vector system containing the mutated essential gene, said mutations being silent mutations. Furthermore, the application discloses the use of an antisense molecule directed to an essential gene as a herbicide in particular using an aqueous solution comprising a saccharide such as sucrose, fructose and glucose.

Abstract translation: 本发明涉及通过用包含至少在两个位点具有突变的必需基因的载体转化植物来生产转基因植物材料的方法。 该方法以EPSPS为必需基因为例。 该方法使得可以使用针对所述基因的天然形式的反义分子来选择转化的植物。 本申请还涉及可通过该方法获得的植物，含有突变必需基因的二元载体系统，所述突变是沉默突变。 此外，本申请公开了使用指向必需基因的反义分子作为除草剂，特别是使用包含糖如蔗糖，果糖和葡萄糖的水溶液。

公开(公告)号：US08319526B2

公开(公告)日：2012-11-27

申请号：US12620156

申请日：2009-11-17

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03K5/22

CPC classification number: H03K5/2481

Abstract: A latched comparator circuit comprises an input amplification unit, a buffer unit, and a control unit. The input amplification unit comprises a first and a second input terminal for receiving a first and a second input voltage, respectively, of the latched comparator circuit. The input amplification unit further comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the input amplification unit. In addition, the input amplification unit comprises a reset terminal arranged to receive a reset signal for resetting the input amplification unit. The buffer unit is operatively connected to the first and the second output terminal of the input amplification unit. Furthermore, the buffer unit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the buffer unit. The control unit is operatively connected to the input amplification unit and the buffer unit. The control unit is adapted to generate the reset signal based on the first and the second output voltage of the buffer unit and a clock signal and to generate an output signal of the latched comparator circuit based on the first and the second output voltage of the buffer unit. A method of operating the latched comparator circuit is also disclosed.

Abstract translation: 锁存比较器电路包括输入放大单元，缓冲单元和控制单元。 输入放大单元包括分别用于接收锁存比较器电路的第一和第二输入电压的第一和第二输入端。 输入放大单元还包括分​​别输出输入放大单元的第一和第二输出电压的第一和第二输出端。 此外，输入放大单元包括复位端子，其被配置为接收用于复位输入放大单元的复位信号。 缓冲单元可操作地连接到输入放大单元的第一和第二输出端。 此外，缓冲单元包括用于分别输出缓冲单元的第一和第二输出电压的第一和第二输出端。 控制单元可操作地连接到输入放大单元和缓冲单元。 控制单元适于基于缓冲单元的第一和第二输出电压和时钟信号产生复位信号，并且基于缓冲器的第一和第二输出电压产生锁存比较器电路的输出信号 单元。 还公开了一种操作锁存比较器电路的方法。

公开(公告)号：US08030972B2

公开(公告)日：2011-10-04

申请号：US12620135

申请日：2009-11-17

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: G01R19/00

CPC classification number: H03K3/35613

Abstract: A latched comparator circuit. The latched comparator circuit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the latched comparator circuit. Furthermore, the latched comparator circuit comprises a cross-coupled pair of transistors operatively connected between the first and the second output terminal for providing a positive feedback in the latched comparator circuit. In addition, the latched comparator circuit comprises a reset terminal for receiving a reset signal and reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal. Moreover, the latched comparator circuit comprises a load unit operatively connected to the cross-coupled pair of transistors and a bias circuit arranged to receive the reset signal and to bias the load unit such that a conductivity of the load unit is higher during the second phase of the reset signal than during the first phase of the reset signal, whereby said positive feedback is stronger during the second phase of the reset signal than during the first phase of the reset signal.

Abstract translation: 锁存比较电路。 锁存比较器电路包括分别输出锁存比较器电路的第一和第二输出电压的第一和第二输出端。 此外，锁存比较器电路包括可操作地连接在第一和第二输出端之间的交叉耦合的晶体管对，用于在锁存比较器电路中提供正反馈。 此外，锁存比较器电路包括用于接收复位信号的复位端和用于在复位信号的第一阶段期间平衡第一和第二输出电压的复位电路，并允许电压差在第一和第二 在复位信号的第二阶段期间输出电压。 此外，锁存比较器电路包括可操作地连接到交叉耦合的晶体管对的负载单元和设置成接收复位信号并偏置负载单元的偏置电路，使得负载单元的电导率在第二阶段期间较高 复位信号的复位信号比复位信号的第一阶段期间的复位信号高，由此所述正反馈在复位信号的第二阶段期间比在复位信号的第一阶段期间更强。

公开(公告)号：US07075465B2

公开(公告)日：2006-07-11

申请号：US10509828

申请日：2003-02-24

Applicant: Bengt Jonsson ,  Christer Jansson

Inventor： Bengt Jonsson ,  Christer Jansson

IPC: H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/36

Abstract: An A/D converter includes at least one comparator array (COMP1–COMP7) for flash A/D conversion of an analog signal. Means (CCU, SW1–SW7) provide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC1–DAC7) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC1–DAC7) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.

Abstract translation: A / D转换器包括用于模拟信号的闪存A / D转换的至少一个比较器阵列（COMP 1 -COMP 7）。 方法（CCU，SW 1 -SW 7）为阵列中的每个比较器提供对两个比较器输入端子的公共参考信号。 方法（CCU，DAC 1 -DAC 7）将阵列中的每个比较器强制为相同的逻辑输出状态。 最后，方法（CCU，DAC 1 -DAC 7）通过斜坡信号调整每个比较器的比较器跳变点，直到逻辑输出状态反转。

公开(公告)号：US20050219090A1

公开(公告)日：2005-10-06

申请号：US10509828

申请日：2003-02-24

Applicant: Bengt Jonsson ,  Christer Jansson

Inventor： Bengt Jonsson ,  Christer Jansson

IPC: H03M1/10 ,  H03M1/36 ,  H03M1/00

CPC classification number: H03M1/1061 ,  H03M1/36

Abstract: An A/D converter includes at least one comparator array (COMP1-COMP7) for flash A/D conversion of an analog signal. Means (CCU, SW1-SW7) pro-vide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC1-DAC7) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC1-DAC7) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.

Abstract translation: A / D转换器包括用于模拟信号的闪存A / D转换的至少一个比较器阵列（COMP 1 -COMP 7）。 意思是（CCU，SW 1 -SW 7），对于阵列中的每个比较器，提供两个比较器输入端子的公共参考信号。 方法（CCU，DAC 1 -DAC 7）将阵列中的每个比较器强制为相同的逻辑输出状态。 最后，方法（CCU，DAC 1 -DAC 7）通过斜坡信号调整每个比较器的比较器跳变点，直到逻辑输出状态反转。

公开(公告)号：US06831586B2

公开(公告)日：2004-12-14

申请号：US10683605

申请日：2003-10-10

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03M134

CPC classification number: H03K3/2885

Abstract: A comparator for an analog-to-digital converter comprises an input stage (in+, in−, M1, M2) for receiving an input signal; a bipolar latch stage (Q1, Q2; Q1a-b, Q2a-b) coupled to the input stage for performing a latch decision based on the input signal; means for amplifying the latch output (Va, Vb) to a level suitable for CMOS circuitry; and an output (out+, out−). The means for amplifying includes at least one tapping transistor (Q3, Q4) coupled to the latch stage for, depending on the latch decision, tapping a collector current (Ic2; Ic1) from the latch stage, while leaving the latch decision thereof unaffected, such that a current gain (&bgr;) of the latch stage can be used to amplify a latch bias current (Ia, Ib) of the latch stage to thereby provide for the amplification.

Abstract translation: 用于模数转换器的比较器包括用于接收输入信号的输入级（in，in，M1，M2）; 耦合到输入级的双极锁存级（Q1，Q2; Q1a-b，Q2a-b），用于基于输入信号执行锁存判定; 用于将锁存器输出（Va，Vb）放大到适合于CMOS电路的电平的装置; 和一个输出（out +，out-）。 用于放大的装置包括耦合到锁存级的至少一个抽头晶体管（Q3，Q4），用于根据锁存器判定从闩锁级分接集电极电流（Ic2; Ic1），同时使锁存器决定不受影响， 使得锁存级的电流增益（β）可以用于放大锁存级的锁存器偏置电流（Ia，Ib），从而提供放大。

公开(公告)号：US08922406B2

公开(公告)日：2014-12-30

申请号：US14118412

申请日：2012-03-16

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/0692 ,  H03M1/1057 ,  H03M1/468

Abstract: A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, is disclosed. For at least an i:th bit bL, the corresponding bit weight wi is less than the sum of the bit weights Wj, j=0, 1, . . . , i−1 corresponding to the bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi. The method comprises sampling a first electrical value representative of the bit weight wi; performing a first analog-to-digital, A/D, conversion using the bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi to obtain a first digital word of said bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi representing said first electrical value; and estimating the value of the bit weight Wi expressed in terms of the bit weights Wj. j=0, 1, . . . , i−1 corresponding to the bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi based at least on said first digital word, wherein the resulting estimated value of the bit weight wi is one of the at least one calibration value. A control unit, a redundant ADC and a computer program are also disclosed.

Abstract translation: 公开了一种确定冗余模数转换器ADC的至少一个校准值的方法。 对于至少第i位bL，对应的位权重wi小于位权重Wj，j = 0,1的总和。 。 。 ，对应于比特bj，j = 0,1，...的i-1。 。 。 ，i-1比位bi的意义不大。 该方法包括对表示比特重量wi的第一电值进行采样; 使用位bj，j = 0,1，进行第一个模数转换，A / D转换。 。 。 ，i-1比位bi具有较小的显着性，以获得所述位bj，j = 0,1的第一数字字。 。 。 i-1，比代表所述第一电值的位bi更不重要; 并且估计以比特权重Wj表示的比特权重Wi的值。 j = 0,1，... 。 。 ，对应于比特bj，j = 0,1，...的i-1。 。 。 ，i-1至少基于所述第一数字字，比所述位bi的重要性低，其中所述位权重wi的所得到的估计值是所述至少一个校准值之一。 还公开了控制单元，冗余ADC和计算机程序。

公开(公告)号：US20110204978A1

公开(公告)日：2011-08-25

申请号：US12993145

申请日：2009-05-25

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03F3/45

CPC classification number: H03F3/45753 ,  H03F2203/45292 ,  H03F2203/45444 ,  H03F2203/45538 ,  H03F2203/45634

Abstract: A comparator circuit (5) comprising a fully differential main amplifier unit (10, 10b). The main amplifier unit (10, 10b) comprises a control port and is adapted to control a bias current of a first branch of the main amplifier unit (10, 10b) and/or a bias current of a second branch of the main amplifier unit (10, 10b) in response to one or more control voltages supplied to the control port of the main amplifier unit (10, 10b). The comparator circuit (5) comprises circuitry (60) for balancing the voltages at the positive and negative input terminals (12a, 12b) of the main amplifier unit (10, 10b) during a first clock phase of the comparator circuit (5). Furthermore, the comparator circuit (10, 10a) comprises a switched-capacitor accumulator unit with a differential input. The switched-capacitor accumulator unit is operatively connected to the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) for sampling voltages at the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) during the first clock phase, and operatively connected to the control port of the main amplifier unit (10, 10b) for supplying said one or more control voltages.

Abstract translation: 一种包括全差分主放大器单元（10,10b）的比较器电路（5）。 主放大器单元（10,10b）包括控制端口，并且适于控制主放大器单元（10,10b）的第一支路的偏置电流和/或主放大器单元的第二支路的偏置电流 （10,10b），响应于提供给主放大器单元（10,10b）的控制端口的一个或多个控制电压。 比较器电路（5）包括用于在比较器电路（5）的第一时钟相位期间平衡主放大器单元（10,10b）的正和负输入端（12a，12b）处的电压的电路（60）。 此外，比较器电路（10,10a）包括具有差分输入的开关电容器累加器单元。 开关电容器蓄电单元可操作地连接到主放大器单元（10,10b）的正输出端和负输出端（14a，14b），用于对主放大器的正负输出端（14a，14b）进行采样电压 单元（10,10b），并且可操作地连接到主放大器单元（10,10b）的控制端口，用于提供所述一个或多个控制电压。