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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08748959B2

    公开(公告)日：2014-06-10

    申请号：US12751245

    申请日：2010-03-31

    申请人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    发明人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    IPC分类号： H01L27/108 ,  H01L21/762

    CPC分类号： H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

    摘要： A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

    摘要翻译： 公开了一种半导体存储器件。 在一个特定的示例性实施例中，半导体存储器件包括以行和列的阵列排列的多个存储器单元。 每个存储单元可以包括连接到沿第一取向延伸的源极线的第一区域。 每个存储单元还可以包括连接到延伸第二取向的位线的第二区域。 每个存储器单元还可以包括与字线间隔开并且电容耦合到字线的主体区域，其中所述主体区域电浮动并且设置在所述第一区域和所述第二区域之间。 半导体器件还可以包括在第一取向上延伸的第一阻挡壁和在第二取向上延伸并与第一阻挡壁相交的第二阻挡壁，以形成配置成容纳多个存储单元中的每一个的沟槽区。

    TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE 有权
    提供半导体存储器件的技术

    公开(公告)号：US20100259964A1

    公开(公告)日：2010-10-14

    申请号：US12751245

    申请日：2010-03-31

    申请人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I. Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    发明人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I. Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    IPC分类号： G11C5/06

    CPC分类号： H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

    摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

    摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。 每个存储单元可以包括连接到沿第一取向延伸的源极线的第一区域。 每个存储单元还可以包括连接到延伸第二取向的位线的第二区域。 每个存储器单元还可以包括与字线间隔开并且电容耦合到字线的主体区域，其中所述主体区域电浮动并且设置在所述第一区域和所述第二区域之间。 半导体器件还可以包括沿阵列的第一取向延伸的第一阻挡壁和在阵列的第二取向延伸并且与第一阻挡壁相交的第二阻挡壁，以形成沟槽区域，该沟槽区域被配置为容纳多个 的记忆细胞。

    Resistive Devices and Methods of Operation Thereof
    3.
    发明申请
    Resistive Devices and Methods of Operation Thereof 有权
    电阻器件及其操作方法

    公开(公告)号：US20140003125A1

    公开(公告)日：2014-01-02

    申请号：US13610690

    申请日：2012-09-11

    申请人： Foroozan Sarah Koushan ,  Michael A. Van Buskirk

    发明人： Foroozan Sarah Koushan ,  Michael A. Van Buskirk

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0092 ,  G11C2213/74 ,  G11C2213/79

    摘要： In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

    摘要翻译： 根据本发明的实施例，一种操作电阻式交换设备的方法包括：在具有第一接入终端的接入设备的第一接入终端和第二接入终端上应用包括脉冲的信号。 第二接入终端耦合到两端电阻式交换设备的第一终端。 电阻式开关装置具有第一端子和第二端子。 电阻式开关装置具有第一状态和第二状态。 脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡，在第二时间段内从第二电压到第三电压的第二斜坡，以及从第三电压到第四电压的第三斜坡 第三个时期。 第二斜坡和第三斜坡与第一坡道具有相反的斜坡。 第一时间段和第二时间段的总和小于第三时间段。

    Techniques for providing a semiconductor memory device
    4.
    发明授权
    Techniques for providing a semiconductor memory device 有权
    提供半导体存储器件的技术

    公开(公告)号：US08547738B2

    公开(公告)日：2013-10-01

    申请号：US13047097

    申请日：2011-03-14

    申请人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

    发明人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

    IPC分类号： G11C11/34

    CPC分类号： H01L27/10802 ,  G11C7/00 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1095 ,  H01L29/7841

    摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

    摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。 每个存储单元包括电容耦合到至少一个字线并且设置在第一区域和第二区域之间的第一区域，第二区域和体区域。 每个存储单元还包括第三区域，其中第三区域可以掺杂不同于第一区域，第二区域和体区域。

    Techniques for providing a direct injection semiconductor memory device
    5.
    发明授权
    Techniques for providing a direct injection semiconductor memory device 有权
    提供直接注入半导体存储器件的技术

    公开(公告)号：US08315099B2

    公开(公告)日：2012-11-20

    申请号：US12844477

    申请日：2010-07-27

    申请人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    发明人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    IPC分类号： G11C16/04

    CPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

    摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

    摘要翻译： 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。 多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。 多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一 其他。

    TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
    提供直接注入半导体存储器件的技术

    公开(公告)号：US20110019482A1

    公开(公告)日：2011-01-27

    申请号：US12844477

    申请日：2010-07-27

    申请人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    发明人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    IPC分类号： G11C16/04

    CPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

    摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

    摘要翻译： 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。 多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。 多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一 其他。

    Adaptive detection of threshold levels in memory
    7.
    发明授权
    Adaptive detection of threshold levels in memory 失效
    内存阈值水平的自适应检测

    公开(公告)号：US07672161B2

    公开(公告)日：2010-03-02

    申请号：US11742371

    申请日：2007-04-30

    申请人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

    发明人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

    IPC分类号： G11C11/03

    CPC分类号： G11C11/5642

    摘要： Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

    摘要翻译： 介绍了便于从存储器访问数据的系统，方法和/或设备。 可以采用自适应检测部件来减少或最小化检测误差，并且在读取操作期间区分存储在存储器单元中的信息。 解码器组件可以包括自适应检测组件，其可以采用自适应林德 - 布佐灰色（LBG）算法。 解码器组件可以在读取操作期间从存储器位置接收与当前级别相关联的信息，并且可以分析和处理这样的信息。 自适应检测组件可以接收经处理的信息，并且与其他信息一起可以使用迭代LBG算法来处理这样的信息，直到确定重建级别和对应的阈值级别为止。 可以将这样的重建级别和/或阈值级别与与从存储器位置读取的信息相关联的值进行比较，以确定存储器位置中的数据的数据值。

    Flash memory array with dual function control lines and asymmetrical source and drain junctions
    9.
    发明授权
    Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
    具有双功能控制线和不对称源极和漏极结的闪存阵列

    公开(公告)号：US06492675B1

    公开(公告)日：2002-12-10

    申请号：US09008162

    申请日：1998-01-16

    申请人： Michael A. Van Buskirk ,  Chi Chang

    发明人： Michael A. Van Buskirk ,  Chi Chang

    IPC分类号： H01L2972

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.

    摘要翻译： 通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。 在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。 所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

    Temperature-compensated bias generator
    10.
    发明授权
    Temperature-compensated bias generator 有权
    温度补偿偏置发生器

    公开(公告)号：US06205074B1

    公开(公告)日：2001-03-20

    申请号：US09610764

    申请日：2000-07-06

    申请人： Michael A. Van Buskirk ,  Bhimachar Venkatesh

    发明人： Michael A. Van Buskirk ,  Bhimachar Venkatesh

    IPC分类号： G11C700

    CPC分类号： G11C5/145 ,  G11C16/30

    摘要： The present invention discloses methods and systems for generating a bias voltage during an Automatic Program Disturb Erase Verify (APDEV) operation in a memory device. During the APDEV operation, a predetermined supply voltage is generated by a regulated power supply. The predetermined supply voltage is directed to a temperature-compensated bias generator circuit. The temperature-compensated bias generator circuit is activated to generate the bias voltage based on the operating temperature of the memory device.

    摘要翻译： 本发明公开了在存储器件中的自动程序干扰擦除验证（APDEV）操作期间产生偏置电压的方法和系统。 在APDEV操作期间，通过稳压电源产生预定的电源电压。 预定的电源电压被引导到温度补偿偏置发生器电路。 温度补偿偏置发生器电路被激活以基于存储器件的工作温度产生偏置电压。