公开(公告)号：US06984556B2

公开(公告)日：2006-01-10

申请号：US10483423

申请日：2002-06-24

申请人： Christian Drabe ,  Jana Haensel ,  Anke Krasemann ,  Barbara Lorenz ,  Thomas Morgenstern ,  Torsten Schneider ,  Bruno Spuler

发明人： Christian Drabe ,  Jana Haensel ,  Anke Krasemann ,  Barbara Lorenz ,  Thomas Morgenstern ,  Torsten Schneider ,  Bruno Spuler

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L21/31116

摘要： A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF4/SiF4/O2 chemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses C4F8 chemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.

摘要翻译： 使用两步蚀刻工艺在沟槽电容器的上部形成垂直环形氧化物。 第一步使用CF 4 / SiF 4 / O 2化学物质，并且当沟槽内的套环的底部打开时结束，尽管薄 氧化物层仍然保留在PAD氮化物的表面上。 第二蚀刻步骤使用C 4 S 8 N 8化学物质完全除去剩余的氧化硅层。 该方法在环氧化物的最上部提供了PAD-氮化物层的厚度均匀性和足够的环氧化物厚度。 该工艺适用于制造用于DRAM器件的深沟槽电容器。

公开(公告)号：US06855596B2

公开(公告)日：2005-02-15

申请号：US10715019

申请日：2003-11-17

申请人： Gabriele Fichtl ,  Jana Haensel ,  Thomas Metzdorf ,  Thomas Morgenstern

发明人： Gabriele Fichtl ,  Jana Haensel ,  Thomas Metzdorf ,  Thomas Morgenstern

IPC分类号： H01L27/108 ,  H01L21/762 ,  H01L21/8242

CPC分类号： H01L27/10861 ,  H01L21/76224 ,  Y10S438/964

摘要： A method for manufacturing a trench capacitor includes the step of etching a shallow isolation trench in a two-step process flow. During a first etching step, an etch chemistry based on chlorine or bromine performs a highly selective etch for silicon. During a second step, the etch chemistry is based on SiF4 and O2 which rather equally etches polysilicon and the collar isolation. On top of the wafer, the deposition of silicon oxide on the hard mask predominates and avoids an erosion of the hard mask. On the bottom of the trench the conformal etching of polysilicon and collar isolation predominates. The method provides an economic process flow and is suitable for small feature sizes.

摘要翻译： 一种用于制造沟槽电容器的方法包括在两步工艺流程中蚀刻浅隔离沟槽的步骤。 在第一蚀刻步骤期间，基于氯或溴的蚀刻化学品对硅进行高选择性蚀刻。 在第二步骤中，蚀刻化学基于SiF 4和O 2，其相当地同时蚀刻多晶硅和套环隔离。 在晶片的顶部，氧化硅在硬掩模上的沉积占优势，并避免了硬掩模的侵蚀。 在沟槽的底部，多晶硅和环状隔离的保形蚀刻占优势。 该方法提供经济的工艺流程，适用于小尺寸。

公开(公告)号：US06852639B2

公开(公告)日：2005-02-08

申请号：US10210757

申请日：2002-07-31

申请人： Matthias Rudolph ,  Jens Stolze ,  Thomas Morgenstern ,  Jana Haensel

发明人： Matthias Rudolph ,  Jens Stolze ,  Thomas Morgenstern ,  Jana Haensel

IPC分类号： H01L21/00 ,  H01L21/308 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01L21/3086 ,  H01L21/31105

摘要： The present invention provides a processing method that changes the given and unfavorable surface contour of a material layer to a predetermined, more favorable surface contour at least along a selected radial direction of the workpiece. Due to the fact that the etch process included into the processing method affects the whole workpiece simultaneously, a high throughput is achievable and the etching method is easily applied in an industrial setting, for example for the mass production of semiconductor products.

摘要翻译： 本发明提供了一种处理方法，其至少沿着所选择的工件的径向方向将材料层的给定和不利的表面轮廓改变到预定的更有利的表面轮廓。 由于包括在处理方法中的蚀刻工艺同时影响整个工件，可以实现高生产率，并且在工业设置中容易地应用蚀刻方法，例如用于大量生产半导体产品。

公开(公告)号：US06593242B2

公开(公告)日：2003-07-15

申请号：US10223038

申请日：2002-08-16

申请人： Thomas Morgenstern

发明人： Thomas Morgenstern

IPC分类号： H01L21311

CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L21/763 ,  H01L28/20

摘要： The invention is directed to a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes the following steps: uniformly etching the polysilicon overfill layer; stopping the etching before the polysilicon layer is completely removed from the surface of the integrated circuit; and recess etching the polysilicon layer with microtrenching properties for forming a substantially planar recess near the top of the at least one trench.

摘要翻译： 本发明涉及一种用于在集成电路中的至少一个多晶硅过填充沟槽中形成凹陷的工艺。 该方法包括以下步骤：均匀蚀刻多晶硅过填充层; 在多晶硅层从集成电路的表面完全去除之前停止蚀刻; 并且用微切削特性对多晶硅层进行凹槽蚀刻，以在至少一个沟槽的顶部附近形成基本平坦的凹槽。