公开(公告)号：US20110309423A1

公开(公告)日：2011-12-22

申请号：US13218188

申请日：2011-08-25

申请人： Christian Foerster ,  Georg Ehrentraut ,  Frank Pfirsch ,  Thomas Raker

发明人： Christian Foerster ,  Georg Ehrentraut ,  Frank Pfirsch ,  Thomas Raker

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/331 ,  H01L29/788

CPC分类号： H01L29/4236 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.

摘要翻译： 公开了一种具有沟槽栅的半导体器件及其制造方法。 一个实施例包括第一半导体区域和第二半导体区域，第一半导体区域和第二半导体区域之间的半导体主体区域以及布置在沟槽中并且通过绝缘层与半导体本体分离的栅极，其中沟槽具有 至少从所述半导体表面延伸到比所述第一半导体区域的深度大的深度的顶部沟槽部分，其中所述沟槽还具有在所述顶部沟槽部分之后延伸的底部沟槽部分，所述顶部沟槽部分至少直到所述第二半导体 并且其中顶部沟槽部分具有第一横向尺寸，并且底部沟槽部分具有大于第一横向尺寸的第二横向尺寸。

公开(公告)号：US20080179666A1

公开(公告)日：2008-07-31

申请号：US12019295

申请日：2008-01-24

申请人： Christian Foerster ,  Georg Ehrentraut ,  Frank Pfirsch ,  Thomas Raker

发明人： Christian Foerster ,  Georg Ehrentraut ,  Frank Pfirsch ,  Thomas Raker

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4236 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.

摘要翻译： 公开了一种具有沟槽栅的半导体器件及其制造方法。 一个实施例包括第一半导体区域和第二半导体区域，第一半导体区域和第二半导体区域之间的半导体主体区域以及布置在沟槽中并且通过绝缘层与半导体本体分离的栅极，其中沟槽具有 至少从所述半导体表面延伸到比所述第一半导体区域的深度大的深度的顶部沟槽部分，其中所述沟槽还具有在所述顶部沟槽部分之后延伸的底部沟槽部分，所述顶部沟槽部分至少直到所述第二半导体 并且其中顶部沟槽部分具有第一横向尺寸，并且底部沟槽部分具有大于第一横向尺寸的第二横向尺寸。

公开(公告)号：US08482062B2

公开(公告)日：2013-07-09

申请号：US13610240

申请日：2012-09-11

申请人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

发明人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397

摘要： A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

摘要翻译： 半导体器件包括从表面延伸到半导体本体中的第一沟槽和第二沟槽。 第一导电类型的主体区域邻接第一沟槽的第一侧壁和第二沟槽的第一侧壁，主体区域包括邻近源极结构的沟道部分，并且被配置为通过栅极结构来控制其导电性 。 通道部分形成在第二沟槽的第一侧壁处，并且不形成在第一沟槽的第一侧壁处。 第一导电类型的电浮动半导体区域邻接第一沟槽，并且具有位于半导体本体内比底体区域的底侧更深的底侧。

公开(公告)号：US08264033B2

公开(公告)日：2012-09-11

申请号：US12506844

申请日：2009-07-21

申请人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

发明人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397

摘要： A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

摘要翻译： 半导体器件包括从表面延伸到半导体本体中的第一沟槽和第二沟槽。 第一导电类型的主体区域邻接第一沟槽的第一侧壁和第二沟槽的第一侧壁，主体区域包括邻近源极结构的沟道部分，并且被配置为通过栅极结构来控制其导电性 。 通道部分形成在第二沟槽的第一侧壁处，并且不形成在第一沟槽的第一侧壁处。 第一导电类型的电浮动半导体区域邻接第一沟槽，并且具有位于半导体本体内比底体区域的底侧更深的底侧。

公开(公告)号：US20130001640A1

公开(公告)日：2013-01-03

申请号：US13610240

申请日：2012-09-11

申请人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

发明人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

IPC分类号： H01L29/739

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397

摘要： A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

摘要翻译： 半导体器件包括从表面延伸到半导体本体中的第一沟槽和第二沟槽。 第一导电类型的主体区域邻接第一沟槽的第一侧壁和第二沟槽的第一侧壁，主体区域包括邻近源极结构的沟道部分，并且被配置为通过栅极结构来控制其导电性 。 通道部分形成在第二沟槽的第一侧壁处，并且不形成在第一沟槽的第一侧壁处。 第一导电类型的电浮动半导体区域邻接第一沟槽，并且具有位于半导体本体内比底体区域的底侧更深的底侧。

公开(公告)号：US20110018029A1

公开(公告)日：2011-01-27

申请号：US12506844

申请日：2009-07-21

申请人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

发明人： Frank Pfirsch ,  Maria Cotorogea ,  Franz Hirler ,  Franz-Josef Niedernostheide ,  Thomas Raker ,  Hans-Joachim Schulze ,  Hans Peter Felsl

IPC分类号： H01L29/739

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397

摘要： A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

摘要翻译： 半导体器件包括从表面延伸到半导体本体中的第一沟槽和第二沟槽。 第一导电类型的主体区域邻接第一沟槽的第一侧壁和第二沟槽的第一侧壁，主体区域包括邻近源极结构的沟道部分，并且被配置为通过栅极结构来控制其导电性 。 通道部分形成在第二沟槽的第一侧壁处，并且不形成在第一沟槽的第一侧壁处。 第一导电类型的电浮动半导体区域邻接第一沟槽，并且具有位于半导体本体内比底体区域的底侧更深的底侧。

公开(公告)号：US20090206440A1

公开(公告)日：2009-08-20

申请号：US12403808

申请日：2009-03-13

申请人： Hans-Joachim Schulze ,  Frank Hille ,  Thomas Raker

发明人： Hans-Joachim Schulze ,  Frank Hille ,  Thomas Raker

IPC分类号： H01L23/58

CPC分类号： H01L29/0615 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.

摘要翻译： 半导体器件具有重掺杂衬底，并且具有设置在衬底上的具有第一导电类型的掺杂硅的上层，上层具有上表面并且包括具有第二相反导电类型的阱区的有源区。 边缘终止区域具有第二导电类型的连接终止延伸区域（JTE）区域，该区域具有远离阱区域延伸的部分，以及设置在连接终端的上表面处的第二导电类型的多个场限制环 延伸区域。

公开(公告)号：US09412854B2

公开(公告)日：2016-08-09

申请号：US12908562

申请日：2010-10-20

申请人： Hans-Peter Felsl ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Thomas Raker

发明人： Hans-Peter Felsl ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Thomas Raker

IPC分类号： H01L27/082 ,  H01L29/739 ,  H01L25/07

CPC分类号： H01L29/7395 ,  H01L25/072 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IGBT module is provided. The IGBT module has at least a first individual IGBT with a first softness during switching-off the IGBT module, and at least a second individual IGBT connected in parallel to the at least one first IGBT. The at least one second individual IGBT has a second softness during switching-off the IGBT module which is different than the first softness. Further a circuit and an electronic power device having two individual IGBTs, which are connected in parallel, are provided.

摘要翻译： 提供IGBT模块。 所述IGBT模块具有至少第一单独的IGBT，所述第一单独IGBT在关断所述IGBT模块期间具有第一柔性，以及至少第二独立IGBT并联连接至所述至少一个第一IGBT。 所述至少一个第二单独IGBT在关断IGBT模块期间具有与第一柔性不同的第二柔软度。 此外，提供了并联连接的具有两个单独的IGBT的电路和电子功率器件。

公开(公告)号：US07952166B2

公开(公告)日：2011-05-31

申请号：US12125496

申请日：2008-05-22

申请人： Franz Hirler ,  Thomas Raker

发明人： Franz Hirler ,  Thomas Raker

IPC分类号： H01L29/739

CPC分类号： H01L29/7397 ,  H01L29/4236 ,  H03K17/567 ,  H03K2217/0036

摘要： A semiconductor device with switch electrode and gate electrode and a method for switching a semiconductor device. One embodiment provides a semiconductor substrate with an emitter region, a drift region, a body region and a source region. The drift region is formed between the emitter and the body region while the body region is formed between the drift and the source region. A first trench structure extends from the source region at least partially into the drift region. The first trench structure includes a gate electrode arranged next to the body region and a switch electrode arranged in portions next to the drift region, wherein the switch and gate electrodes are electrically insulated from each other in the trench structure. A first gate driver is electrically connected to the gate electrode while a second gate driver is electrically connected to the switch gate.

摘要翻译： 具有开关电极和栅电极的半导体器件和用于切换半导体器件的方法。 一个实施例提供具有发射极区域，漂移区域，体区域和源极区域的半导体衬底。 漂移区形成在发射体和体区之间，同时在漂移和源区之间形成体区。 第一沟槽结构至少部分地从源极区域延伸到漂移区域中。 第一沟槽结构包括邻近体区布置的栅电极和布置在漂移区旁边的部分的开关电极，其中开关和栅电极在沟槽结构中彼此电绝缘。 第一栅极驱动器电连接到栅电极，而第二栅极驱动器电连接到开关栅极。

公开(公告)号：US10211057B2

公开(公告)日：2019-02-19

申请号：US13197903

申请日：2011-08-04

申请人： Franz Hirler ,  Anton Mauder ,  Thomas Raker ,  Hans-Joachim Schulze ,  Wolfgang Werner

发明人： Franz Hirler ,  Anton Mauder ,  Thomas Raker ,  Hans-Joachim Schulze ,  Wolfgang Werner

IPC分类号： H01L21/26 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265 ,  H01L29/739 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/32

摘要： A transistor component includes in a semiconductor body a source zone and a drift zone of a first conduction type, and a body zone of a second conduction type complementary to the first conduction type, the body zone arranged between the drift zone and the source zone. The transistor component further includes a source electrode in contact with the source zone and the body zone, a gate electrode adjacent the body zone and dielectrically insulated from the body zone by a gate dielectric layer, and a diode structure connected between the drift zone and the source electrode. The diode structure includes a first emitter zone adjoining the drift zone in the semiconductor body, and a second emitter zone of the first conduction type adjoining the first emitter zone. The second emitter zone is connected to the source electrode and has an emitter efficiency γ of less than 0.7.