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    Photovoltaic system with managed output and method of managing variability of output from a photovoltaic system
    5.
    发明授权
    Photovoltaic system with managed output and method of managing variability of output from a photovoltaic system 有权
    具有管理输出的光伏系统和管理光伏系统输出变化的方法

    公开(公告)号：US08334489B2

    公开(公告)日：2012-12-18

    申请号：US12721372

    申请日：2010-03-10

    申请人： Greg Beardsworth ,  Matt Campbell ,  Steve Kraft ,  Jason Jones

    发明人： Greg Beardsworth ,  Matt Campbell ,  Steve Kraft ,  Jason Jones

    IPC分类号： G01C21/00 ,  F24J2/38

    CPC分类号： H02S40/00 ,  F24S50/20 ,  H02S50/00 ,  H02S50/10 ,  Y02E10/47 ,  Y02E10/52

    摘要： Photovoltaic systems with managed output and methods for managing variability of output from photovoltaic systems are described. A system includes a plurality of photovoltaic modules configured to receive and convert solar energy. The system also includes a sensor configured to determine an orientation for each of the plurality of photovoltaic modules, the orientations based on a maximum output from the photovoltaic system. The system also includes an orientation system configured to alter the orientation of one or more of the plurality of photovoltaic modules to provide a reduced output from the photovoltaic system, the reduced output less than the maximum output.

    摘要翻译： 描述了具有管理输出的光伏系统和管理光伏系统输出变化的方法。 一种系统包括被配置为接收和转换太阳能的多个光伏模块。 该系统还包括被配置为基于来自光伏系统的最大输出来确定多个光伏模块中的每一个的取向的传感器。 该系统还包括被配置为改变多个光伏模块中的一个或多个的取向的取向系统，以提供来自光伏系统的减小的输出，该输出小于最大输出。

    Data Transfer With Single Channel Controller Controlling Plural Transfer Controllers
    7.
    发明申请
    Data Transfer With Single Channel Controller Controlling Plural Transfer Controllers 有权
    数据传输与单通道控制器控制多个传输控制器

    公开(公告)号：US20060259660A1

    公开(公告)日：2006-11-16

    申请号：US11383063

    申请日：2006-05-12

    申请人： Roger Castille ,  Natarajan Seshan ,  Henry C. Nguyen ,  Marco Lazar ,  Jason Jones

    发明人： Roger Castille ,  Natarajan Seshan ,  Henry C. Nguyen ,  Marco Lazar ,  Jason Jones

    IPC分类号： G06F3/00

    CPC分类号： G06F13/28

    摘要： A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.

    摘要翻译： 数据传送控制装置包括信道控制器和多个传送控制器。 信道控制器接收数据传输请求的优先次序和队列。 传输控制器表的事件使得能够调用对应于数据传送请求的传送控制器号码。 多个传送控制器是独立的并且可以同时并行操作。 每个传送控制器包括一读读总线接口和一写写总线接口，在阻塞对干扰设备或地址范围的访问的情况下，与其它总线主机进行仲裁。

    Host port interface
    8.
    发明授权
    Host port interface 失效
    主机端口接口

    公开(公告)号：US06438720B1

    公开(公告)日：2002-08-20

    申请号：US08488394

    申请日：1995-06-07

    申请人： Frederic Boutaud ,  Jason Jones ,  Marc Couvrat ,  Oliver Mougenot ,  Mansoor A. Chishtie

    发明人： Frederic Boutaud ,  Jason Jones ,  Marc Couvrat ,  Oliver Mougenot ,  Mansoor A. Chishtie

    IPC分类号： G01R3128

    CPC分类号： G06F11/24

    摘要： A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

    摘要翻译： 提供了一种用于将处理器与主机处理器进行接口的电路，其具有与处理器相关联的存储器，所述存储器可由处理器或主机处理器可选择地访问，可选择地与存储器和主机处理器互连的多个存储设备，以及 与存储设备和处理器互连的逻辑电路，用于响应于来自处理器的信号将存储设备的至少一部分互连到存储器。 提供了一种集成电路，其具有微处理器，与所述处理器相关联的存储器，所述存储器可由所述微处理器或主机处理器选择性地访问，可选择地与所述存储器和所述主处理器相互连接的多个存储设备，以及与所述主处理器互连的逻辑电路 存储设备并且可与所述处理器互连，用于响应于来自所述处理器的信号将所述存储设备的至少一部分互连到所述存储器。

    Host port interface
    9.
    发明授权
    Host port interface 失效

    公开(公告)号：US5838934A

    公开(公告)日：1998-11-17

    申请号：US471900

    申请日：1995-06-07

    申请人： Frederic Boutaud ,  Jason Jones ,  Marc Couvrat ,  Oliver Mougenot ,  Mansoor A. Chishtie

    发明人： Frederic Boutaud ,  Jason Jones ,  Marc Couvrat ,  Oliver Mougenot ,  Mansoor A. Chishtie

    IPC分类号： G06F13/28 ,  G06F13/38 ,  G06F13/00

    CPC分类号： G06F13/28 ,  G06F13/385

    摘要： A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

    System having registers for receiving data, registers for transmitting data, both at a different clock rate, and control circuitry for shifting the different clock rates
    10.
    发明授权
    System having registers for receiving data, registers for transmitting data, both at a different clock rate, and control circuitry for shifting the different clock rates 失效
    具有用于接收数据的寄存器，用于以不同时钟速率发送数据的寄存器的系统以及用于移位不同时钟速率的控制电路

    公开(公告)号：US5734927A

    公开(公告)日：1998-03-31

    申请号：US489463

    申请日：1995-06-08

    申请人： Frederic Boutaud ,  Marc Couvrat ,  Yves Masse ,  Mansoor A. Chishtie ,  Alain Vallauri ,  Ajay Padgaonkar ,  Jason Jones

    发明人： Frederic Boutaud ,  Marc Couvrat ,  Yves Masse ,  Mansoor A. Chishtie ,  Alain Vallauri ,  Ajay Padgaonkar ,  Jason Jones

    IPC分类号： G06F13/16 ,  G06F13/00

    CPC分类号： G06F13/1673

    摘要： An electronic device for transferring data between a serial port and a memory of a CPU is provided having a plurality of data registers for transferring data between said serial port and said memory in response to a first set of control signals, a data bus connected to said registers and said memory for passing data to and from said memory in response to a portion of said first set of control signals, first control circuitry for generating said first set of control signals and for generating at least one interrupt to said CPU, at least one control register connected to said first control circuitry for providing mode control information to said first control circuitry, a plurality of address registers for storing data address, at least one address generator connected to said address registers for automatically generating addresses in response to a second set of control signals, an address bus connected to said address registers, and second control circuitry connected to said address generator, a portion of said control register and said first control circuitry for generating said second set of control signals.

    摘要翻译： 提供一种用于在CPU的串行端口和存储器之间传送数据的电子设备，其具有多个数据寄存器，用于响应于第一组控制信号在所述串行端口和所述存储器之间传送数据，连接到所述串行端口的数据总线 寄存器和用于响应于所述第一组控制信号的一部分将数据传送到所述存储器的所述存储器，用于产生所述第一组控制信号并用于向所述CPU产生至少一个中断的第一控制电路，至少一个 连接到所述第一控制电路的控制寄存器，用于向所述第一控制电路提供模式控制信息，多个用于存储数据地址的地址寄存器，连接到所述地址寄存器的至少一个地址发生器，用于响应于第二组 控制信号，连接到所述地址寄存器的地址总线，以及连接到所述地址字的第二控制电路 所述控制寄存器的一部分和所述第一控制电路用于产生所述第二组控制信号。