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1.发明授权System and method for compensating the dielectric absorption of a capacitor using the dielectric absorption of another capacitor 有权使用另一电容器的电介质吸收来补偿电容器的介电吸收的系统和方法公开(公告)号：US06294945B1
公开(公告)日：2001-09-25
申请号：US09496566
申请日：2000-02-02
IPC分类号： G06G719
CPC分类号： G06G7/1865
摘要： A system and method, wherein the dielectric absorption of a capacitor is cancelled by a compensating circuit. One embodiment uses a compensation circuit comprising a compensating capacitor with substantially identical characteristics as the capacitor to be compensated in an integrator circuit. The effects of the dielectric absorption of the capacitor in the integrator circuit are reduced or eliminated because the dielectric absorption of the compensating capacitor cancels the dielectric absorption of the capacitor in the integrator circuit. Another embodiment uses compensation circuitry to reduce or eliminate the effects of dielectric absorption in any particular capacitor. The compensation capacitor in the compensation circuitry has a higher rate of dielectric absorption and a lower capacitance value than the capacitor whose dielectric absorption effects are to be reduced or eliminated. In another embodiment, the effects of the dielectric absorption of a capacitor are reduced or eliminated by choosing a compensation capacitor in the compensation circuitry with the same dielectric absorption as the capacitor to be compensated. The dielectric absorption of the compensation capacitor is scaled by the resistors in the compensation circuitry which determine the gain of the amplifier in the compensation circuitry.
摘要翻译： 一种系统和方法，其中电容器的介电吸收由补偿电路消除。 一个实施例使用补偿电路，其包括具有基本相同特性的补偿电容器作为要在积分器电路中补偿的电容器。 由于补偿电容器的电介质吸收抵消积分电路中的电容器的介电吸收，所以减小或消除了积分器电路中电容器的介电吸收的影响。 另一实施例使用补偿电路来减少或消除任何特定电容器中介质吸收的影响。 补偿电路中的补偿电容器具有比电介质吸收效应要降低或消除的电容器更高的介电吸收率和较低的电容值。 在另一个实施例中，通过在具有与要补偿的电容器相同的介电吸收的补偿电路中选择补偿电容来减小或消除电容器的电介质吸收的影响。 补偿电容器的介电吸收由补偿电路中的电阻器来确定放大器在补偿电路中的增益。
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2.发明申请Method and Apparatus for Calibration of Successive Approximation Register Analog-to-Digital Converters 有权用于校正连续近似寄存器模数转换器的方法和装置公开(公告)号：US20150002321A1
公开(公告)日：2015-01-01
申请号：US13931767
申请日：2013-06-28
申请人： Yan Zhou , Clayton Daigle , Shouli Yan , Mohamed Elsayed
发明人： Yan Zhou , Clayton Daigle , Shouli Yan , Mohamed Elsayed
IPC分类号： H03M1/06
CPC分类号： H03M1/0617 , H03M1/1047 , H03M1/466
摘要： A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.
摘要翻译： 逐次逼近寄存器（SAR）ADC包括包括第一和第二输入，控制输入以及第一和第二输出的SAR比较器电路。 SAR比较器电路还包括耦合到第一和第二输入的多个电容器，并且包括被配置为将多个电容器耦合到第一电压和第二电压之一的多个开关。 SAR ADC还包括耦合到第一和第二输出和SAR比较器的控制输入的校准电路。 校准电路被配置为控制多个开关以选择性地将多个电容器耦合到第一和第二电压之一，以向SAR比较器电路提供校准信号。 校准电路被配置为基于在第一和第二输出处的相应输出信号校准SAR比较器。
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3.发明授权Method and apparatus for calibration of successive approximation register analog-to-digital converters 有权用于校准逐次逼近寄存器模数转换器的方法和装置公开(公告)号：US09041569B2
公开(公告)日：2015-05-26
申请号：US13931767
申请日：2013-06-28
申请人： Yan Zhou , Clayton Daigle , Shouli Yan , Mohamed Elsayed
发明人： Yan Zhou , Clayton Daigle , Shouli Yan , Mohamed Elsayed
IPC分类号： H03M1/06
CPC分类号： H03M1/0617 , H03M1/1047 , H03M1/466
摘要： A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.
摘要翻译： 逐次逼近寄存器（SAR）ADC包括包括第一和第二输入，控制输入以及第一和第二输出的SAR比较器电路。 SAR比较器电路还包括耦合到第一和第二输入的多个电容器，并且包括被配置为将多个电容器耦合到第一电压和第二电压中的一个的多个开关。 SAR ADC还包括耦合到第一和第二输出和SAR比较器的控制输入的校准电路。 校准电路被配置为控制多个开关以选择性地将多个电容器耦合到第一和第二电压之一，以向SAR比较器电路提供校准信号。 校准电路被配置为基于在第一和第二输出处的相应输出信号校准SAR比较器。
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4.发明申请Programmable gain instrumentation amplifier including a composite amplifier for level shifting and improved signal-to-noise ratio 有权可编程增益仪表放大器，包括用于电平转换和改善信噪比的复合放大器公开(公告)号：US20050195027A1
公开(公告)日：2005-09-08
申请号：US11108357
申请日：2005-04-18
IPC分类号： H03G3/20
CPC分类号： H03G1/0088
摘要： A PGIA for use in measurement devices (e.g., data acquisition device) including a composite amplifier for level shifting and improved signal-to-noise ratio. The composite amplifier may level shift from a constant common mode voltage to a lower common mode voltage with a large voltage swing. The large output signal swing of the PGIA may allow excellent signal-to-noise ratio. Additionally, input op-amps of the PGIA may be bootstrapped so that their supply rails move according to an input signal of the PGIA. The PGIA may also include protection circuitry to protect components from damage, e.g., due to over-current conditions, and to keep all op-amps in proper closed loop operation. Furthermore, the PGIA may include DA compensation circuitry to cancel some dielectric absorptions effects and improve a step response of the PGIA and CMRR enhancement circuitry to increase symmetry at inputs of the PGIA and improve a CMRR associated with the PGIA.
摘要翻译： 用于测量装置（例如，数据采集装置）的PGIA，其包括用于电平移位的复合放大器和改善的信噪比。 复合放大器可以在具有较大的电压摆幅的情况下从恒定的共模电压电平转换到较低的共模电压。 PGIA的大输出信号摆幅可以提供优异的信噪比。 此外，PGIA的输入运算放大器可能会自举，以使其电源轨根据PGIA的输入信号移动。 PGIA还可以包括保护电路，以保护组件免受例如过电流状况的损坏，并保持所有运算放大器处于适当的闭环运行状态。 此外，PGIA可以包括DA补偿电路，以消除一些介电吸收效应，并改善PGIA和CMRR增强电路的阶跃响应，以增加PGIA输入端的对称性并改善与PGIA相关联的CMRR。
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5.发明申请Calibrating analog-to-digital systems using a precision reference and a pulse-width modulation circuit to reduce local and large signal nonlinearities 有权使用精密参考和脉冲宽度调制电路校准模拟数字系统，以减少本地和大信号非线性公开(公告)号：US20050197796A1
公开(公告)日：2005-09-08
申请号：US11107342
申请日：2005-04-15
CPC分类号： H03M1/1028 , H03M1/12
摘要： A calibration unit and technique for calibrating A/D systems (e.g., data acquisition devices) using a pulse-width modulation (PWM) circuit to reduce nonlinearity. The calibration unit may be coupled to an analog-to-digital module (ADM) of the A/D system. The PWM circuit may generate a calibration signal with intentional ripple, which may exercise a region of a transfer curve of the ADM to reduce local nonlinearities in measurements associated with the calibration of the system. Pulse trains of varying frequency and duty cycle may be generated to sweep the PWM circuit through an ADM range and to calculate an ADM linearity correction function, which may be used to perform gain and offset correction with respect to a best-fit line through an ADM transfer curve to reduce large signal nonlinearities. The PWM circuit may include a resistor divider circuit including a plurality of taps to improve the ability to calibrate small input ranges.
摘要翻译： 用于使用脉冲宽度调制（PWM）电路校准A / D系统（例如，数据采集装置）以减少非线性的校准单元和技术。 校准单元可以耦合到A / D系统的模拟 - 数字模块（ADM）。 PWM电路可以产生具有有意的纹波的校准信号，其可以锻炼ADM的传递曲线的区域以减少与系统的校准相关联的测量中的局部非线性。 可产生变化频率和占空比的脉冲串，以扫描PWM电路通过ADM范围，并计算ADM线性校正功能，可用于通过ADM对最佳拟合线进行增益和偏移校正 传递曲线以减小大信号非线性。 PWM电路可以包括包括多个抽头的电阻分压器电路，以提高校准小输入范围的能力。
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6.发明申请公开(公告)号：US20050088229A1
公开(公告)日：2005-04-28
申请号：US11019008
申请日：2004-12-21
CPC分类号： H03F3/45475 , H03F3/211 , H03F3/45928 , H03F2200/228 , H03F2200/261 , H03F2200/447
摘要： A PGIA for use in measurement devices (e.g., data acquisition device) having improved dielectric absorption (DA) compensation and common mode rejection ratio (CMRR). When a step function is applied to an input of the PGIA, a first and a second DA compensation circuit may generate DA compensation signals derived from the step function. The DA compensation signals may combine with an original response of the PGIA to cancel some of the dielectric absorptions effects and improve the overall step response of the PGIA. An input stage of the PGIA may include a CMRR enhancement circuit to increase symmetry at the inputs of the PGIA. The CMRR enhancement circuit may delay an input signal received at a negative input terminal a particular amount such that it is in phase with an input signal received at a positive input terminal of the PGIA, to improve the CMRR.
摘要翻译： 用于具有改善的介电吸收（DA）补偿和共模抑制比（CMRR））的测量装置（例如，数据采集装置）的PGIA。 当对PGIA的输入施加阶梯函数时，第一和第二DA补偿电路可以生成从阶梯函数导出的DA补偿信号。 DA补偿信号可以与PGIA的原始响应相结合以消除一些介电吸收效应并改善PGIA的整体阶跃响应。 PGIA的输入级可以包括增加PGIA输入端的对称性的CMRR增强电路。 CMRR增强电路可以将在负输入端子处接收的输入信号延迟特定量，使得其与在PGIA的正输入端子处接收的输入信号同相，以改善CMRR。
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公开(公告)号：US08730404B2
公开(公告)日：2014-05-20
申请号：US13484475
申请日：2012-05-31
IPC分类号： H04N5/50
CPC分类号： H03K3/356191 , H04N5/455
摘要： In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.
摘要翻译： 在一个实施例中，本发明包括具有接收数据信号的第一输入端和接收时钟信号的第二输入端的锁存电路。 该锁存电路可以具有第一对晶体管，其包括由数据信号门控的第一晶体管和由反相数据信号选通的第二晶体管，以及包括由时钟信号选通的第三和第四晶体管的第二对晶体管。 第一晶体管可以在第一闩锁间节点处耦合到第三晶体管，并且第二晶体管在第二锁存间节点处耦合到第四晶体管。 当时钟信号不活动时，复位电路可以耦合到锁存电路，以将第一和第二锁存器间节点维持在预定电压电平。
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公开(公告)号：US20130321709A1
公开(公告)日：2013-12-05
申请号：US13484475
申请日：2012-05-31
CPC分类号： H03K3/356191 , H04N5/455
摘要： In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.
摘要翻译： 在一个实施例中，本发明包括具有接收数据信号的第一输入端和接收时钟信号的第二输入端的锁存电路。 该锁存电路可以具有第一对晶体管，其包括由数据信号门控的第一晶体管和由反相数据信号选通的第二晶体管，以及包括由时钟信号选通的第三和第四晶体管的第二对晶体管。 第一晶体管可以在第一闩锁间节点处耦合到第三晶体管，并且第二晶体管在第二锁存间节点处耦合到第四晶体管。 当时钟信号不活动时，复位电路可以耦合到锁存电路，以将第一和第二锁存器间节点维持在预定电压电平。
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