公开(公告)号：US20150214094A1

公开(公告)日：2015-07-30

申请号：US14163323

申请日：2014-01-24

申请人： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

发明人： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

IPC分类号： H01L21/768

CPC分类号： H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

摘要翻译： 用于形成在电介质层内具有紧密间距互连结构的互连层的工艺，其中用于形成的互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的电位。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

公开(公告)号：US20160126184A1

公开(公告)日：2016-05-05

申请号：US14931175

申请日：2015-11-03

申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

公开(公告)号：US09209077B2

公开(公告)日：2015-12-08

申请号：US14137588

申请日：2013-12-20

申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

摘要翻译： 描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。 在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。 第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅，并且包括与第一光栅交错的一个或多个牺牲材料。 该方法还涉及在第一硬掩模层之上形成第二硬掩模层。 第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。 该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。 蚀刻涉及去除一个或多个牺牲材料的一部分。

公开(公告)号：US09548269B2

公开(公告)日：2017-01-17

申请号：US14931175

申请日：2015-11-03

申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

IPC分类号： H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L21/311

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

摘要翻译： 描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。 在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。 第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅并且包括与第一光栅交错的一个或多个牺牲材料。 该方法还涉及在第一硬掩模层之上形成第二硬掩模层。 第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。 该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。 蚀刻涉及去除一个或多个牺牲材料的一部分。

公开(公告)号：US20150179513A1

公开(公告)日：2015-06-25

申请号：US14137588

申请日：2013-12-20

申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/033

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

摘要翻译： 描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。 在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。 第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅，并且包括与第一光栅交错的一个或多个牺牲材料。 该方法还涉及在第一硬掩模层之上形成第二硬掩模层。 第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。 该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。 蚀刻涉及去除一个或多个牺牲材料的一部分。

公开(公告)号：US20150179515A1

公开(公告)日：2015-06-25

申请号：US14139363

申请日：2013-12-23

申请人： Christopher J. Jezewski ,  Jasmeet S. Chawla

发明人： Christopher J. Jezewski ,  Jasmeet S. Chawla

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/02126 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

公开(公告)号：US09054164B1

公开(公告)日：2015-06-09

申请号：US14139363

申请日：2013-12-23

申请人： Christopher J. Jezewski ,  Jasmeet S. Chawla

发明人： Christopher J. Jezewski ,  Jasmeet S. Chawla

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/02126 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

摘要翻译： 本发明的实施例描述了用于半导体器件的低电容互连结构以及用于制造这种器件的方法。 根据本发明的实施例，低电容互连结构包括层间电介质（ILD）。 第一和第二互连线以交替图案设置在ILD中。 第一互连线的顶表面可以在第二互连线的顶表面下方凹入。 第一互连线的凹槽中的增加减小相邻互连之间的线间电容。 另外的实施例包括利用不同的介电材料作为第一和第二互连线之上的蚀刻帽。 在蚀刻过程中，不同的材料可能具有彼此高的选择性。 因此，增加了对各个互连线的接触的对准预算。