公开(公告)号：US08769356B2

公开(公告)日：2014-07-01

申请号：US13570568

申请日：2012-08-09

申请人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

发明人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

IPC分类号： G11C29/00 ,  G11C29/24

CPC分类号： G11C29/24 ,  G11C29/00 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

摘要： A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

摘要翻译： 存储器件包括存储单元阵列和坏页映射。 存储单元阵列包括以页和列排列的多个存储单元，其中存储单元阵列被划分为与存储单元阵列对应的第一存储块和第二存储块。 坏页面映射存储指示第一存储器块的每个页面是好是坏的页面位置信息。 根据坏页位置信息，第一存储块的失败页地址被第二存储块的通过页地址替换。

公开(公告)号：US08873324B2

公开(公告)日：2014-10-28

申请号：US13240049

申请日：2011-09-22

申请人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

发明人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

IPC分类号： G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/40622 ,  G11C11/408

摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.

摘要翻译： 生成具有刷新周期的刷新地址，以刷新刷新的存储器件。 当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。 当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。 仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。 在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

公开(公告)号：US20120300568A1

公开(公告)日：2012-11-29

申请号：US13240049

申请日：2011-09-22

申请人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

发明人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

IPC分类号： G11C11/402

CPC分类号： G11C11/40618 ,  G11C11/40622 ,  G11C11/408

摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.

摘要翻译： 生成具有刷新周期的刷新地址，以刷新刷新的存储器件。 当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。 当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。 仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。 在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

公开(公告)号：US08010765B2

公开(公告)日：2011-08-30

申请号：US11775780

申请日：2007-07-10

申请人： Joo-Sun Choi ,  Won-Chang Jung ,  Hi-Choon Lee ,  Sung-Min Yim ,  Chul-Woo Park ,  Won-Il Bae

发明人： Joo-Sun Choi ,  Won-Chang Jung ,  Hi-Choon Lee ,  Sung-Min Yim ,  Chul-Woo Park ,  Won-Il Bae

IPC分类号： G06F12/00

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

摘要翻译： 在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。 半导体存储器件可以包括控制单元和等待时间控制单元。 控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。 延迟控制单元可以响应于等待时间控制信号来控制等待时间值。 半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。

公开(公告)号：US08279652B2

公开(公告)日：2012-10-02

申请号：US12708049

申请日：2010-02-18

申请人： Joo-Sun Choi

发明人： Joo-Sun Choi

IPC分类号： G11C5/06

CPC分类号： G11C5/04 ,  G11C7/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected together, typically by point-to-point links. When the memory system configuration is such that at least one of the ports in at least one of the memory devices is not used, one or more other ports can use the pins that may otherwise have been used by the unused ports. As a result, a set of reconfigurable, shared pins is defined in which two ports share the pins. The port that is not being used in a particular application for the memory device is not connected to the shared pins, and another port that is being used in the application is connected to the shared pins. This allows for the used of fewer package pins and, consequently, reduced package size.

摘要翻译： 存储器系统和存储器模块包括多个存储器件，每个存储器件具有多个，例如， 四个用于发送和接收命令信号的端口，写数据信号和读数据信号。 其中一个存储设备连接到主机或控制器，其余存储器通常通过点对点链路连接在一起。 当存储器系统配置使得至少一个存储器设备中的至少一个端口不被使用时，一个或多个其他端口可以使用另外可能由未使用的端口使用的引脚。 因此，定义了一组可重新配置的共享引脚，其中两个端口共享引脚。 在存储器件的特定应用中未使用的端口未连接到共享引脚，并且应用中正在使用的另一个端口连接到共享引脚。 这允许使用更少的封装引脚，从而减少封装尺寸。

公开(公告)号：US08161349B2

公开(公告)日：2012-04-17

申请号：US12183552

申请日：2008-07-31

申请人： Hoe-Ju Chung ,  Joo-Sun Choi ,  Ken S. Lim

发明人： Hoe-Ju Chung ,  Joo-Sun Choi ,  Ken S. Lim

IPC分类号： H03M13/00

CPC分类号： H03M13/091 ,  H03M13/6575

摘要： Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.

摘要翻译： 提供了一种数据并行接收器，包括用于从外部接收串行数据作为分组的输入信号接收器，对串行数据进行采样，以输入顺序对准采样数据，并将对准的数据转换为并行数据以输出并行数据，循环冗余 检查（CRC）部分计算器，用于接收并行数据，根据输入顺序将并行数据分组成组，并对每个组执行部分CRC计算，以顺序输出多个部分CRC计算结果，以及CRC部分 用于接收多个部分CRC计算结果的计算合并，并将部分CRC计算结果合并到输出CRC计算数据。

公开(公告)号：US07930492B2

公开(公告)日：2011-04-19

申请号：US12006766

申请日：2008-01-04

申请人： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

发明人： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G11C7/1075

摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.

摘要翻译： 存储器系统基于堆栈位置信息选择性地设置信令模式。 存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。 在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。 因此，存储系统具有降低的功耗。

公开(公告)号：US20070106838A1

公开(公告)日：2007-05-10

申请号：US11504421

申请日：2006-08-15

申请人： Joo-Sun Choi

发明人： Joo-Sun Choi

IPC分类号： G06F13/28

CPC分类号： G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C2211/4061

摘要： A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices. The refresh control circuit classifies the semiconductor memory devices into first and second groups and sets an auto refresh interval of the semiconductor memory devices belong to the first group and an auto refresh interval of the semiconductor memory devices belong to the second group different from each other.

摘要翻译： 控制多个半导体存储器件的存储器控​​制器包括控制半导体存储器件的刷新操作的刷新控制电路。 刷新控制电路将半导体存储器件分为第一组和第二组，并且设置属于第一组的半导体存储器件的自动刷新间隔，并且属于第二组的半导体存储器件的自动刷新间隔彼此不同。

公开(公告)号：US08817549B2

公开(公告)日：2014-08-26

申请号：US13478774

申请日：2012-05-23

申请人： Choong-Sun Shin ,  Joo-Sun Choi

发明人： Choong-Sun Shin ,  Joo-Sun Choi

IPC分类号： G11C7/10

CPC分类号： G11C5/04 ,  G11C5/025 ,  G11C7/10 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4097

摘要： A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2^K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

摘要翻译： 半导体存储器件包括形成在一个芯片上的多个存储器区域，每个存储器区域具有多个易失性存储器单元，其形成为2K比特的密度或容量，其中K是大于或等于的整数 以及用于输入和输出易失性存储器单元的数据的多个输入/输出（I / O）端子，以及控制用于将数据写入存储区域的写入操作的至少一个外围区域，以及用于 基于从外部输入的命令和地址从存储器区域读取数据。 因此，存储区域的总体或整个密度对应于非标准（或“临时”）密度，使得半导体存储器件可具有临时密度。

公开(公告)号：US20110289269A1

公开(公告)日：2011-11-24

申请号：US13153850

申请日：2011-06-06

申请人： Joo-Sun Choi

发明人： Joo-Sun Choi

IPC分类号： G06F12/00

CPC分类号： G06F12/0802

摘要： A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.

摘要翻译： 存储器系统包括用于产生控制信号的控制器和用于从控制器接收控制信号的主存储器。 次存储器耦合到主存储器，辅存储器适于从主存储器接收控制信号。 控制信号定义要由主存储器和次存储器之一执行的背景操作以及由另一个主存储器和次存储器执行的前景操作。 主存储器和辅助存储器通过点对点链路连接。 主存储器和次存储器之间的至少一个链路可以是至少部分序列化的链路。 主存储器和次存储器中的至少一个可以包括机载内部高速缓冲存储器。