公开(公告)号：US08456906B2

公开(公告)日：2013-06-04

申请号：US13306678

申请日：2011-11-29

申请人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

发明人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/349

摘要： An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state.

摘要翻译： 一种具有多个存储单元的存储器件的操作方法，包括：通过第一字线电压读取多个存储器单元以获得第一数量的第一逻辑状态; 通过第二字线电压读取多个存储器单元以获得第二数量的第一逻辑状态，第二字线电压不同于第一字线电压; 并且如果第一逻辑状态的第一数目等于第一逻辑状态的第二数量，则使用第二字线电压作为目标字线电压。

公开(公告)号：US08259484B2

公开(公告)日：2012-09-04

申请号：US12768620

申请日：2010-04-27

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho

IPC分类号： G11C5/06

CPC分类号： G11C8/12 ,  G11C5/02 ,  Y10T29/49002

摘要： A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the scan ID on the shared input is compared with the unique first ID stored on the die. Upon detecting a match, circuitry on the die is enabled for a period of time to write an access ID in nonvolatile memory, whereby one of the die in the multi-chip package is enabled at a time. Also, the shared input is used to write a free access ID in nonvolatile memory on the one enabled die in the set. The unique first IDs can be stored during a wafer level sort process.

摘要翻译： 具有共享输入和唯一访问ID的芯片的多芯片封装。 一个独特的第一个ID被分配并存储在模具中的裸片上。 一组芯片安装在多芯片封装中。 通过在共享输入上应用一系列扫描ID来分配自由访问ID。 在每个管芯上，将共享输入上的扫描ID与存储在管芯上的唯一的第一个ID进行比较。 在检测到匹配时，芯片上的电路被使能一段时间以将访问ID写入非易失性存储器中，从而一次启用多芯片封装中的一个管芯。 此外，共享输入用于在集合中的一个启用的裸片上的非易失性存储器中写入可用访问ID。 唯一的第一个ID可以在晶片级分类过程中存储。

公开(公告)号：US08239619B2

公开(公告)日：2012-08-07

申请号：US12833305

申请日：2010-07-09

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Hsiang-Pang Li

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Hsiang-Pang Li

IPC分类号： G06F12/00 ,  G06F9/26

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access.

摘要翻译： 利用一次擦除一次程序的渐进式索引结构的技术管理闪速存储器件中的数据，这避免了每次更新存储在闪速存储器件中的数据时执行扇区擦除操作。 结果，在需要扇区擦除操作之前可以执行大量写入操作。 因此，基于块的闪存可用于高速字节访问。

公开(公告)号：US20120069671A1

公开(公告)日：2012-03-22

申请号：US13306678

申请日：2011-11-29

申请人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

发明人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

IPC分类号： G11C16/26

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/349

摘要： An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state.

摘要翻译： 一种具有多个存储单元的存储器件的操作方法，包括：通过第一字线电压读取多个存储器单元以获得第一数量的第一逻辑状态; 通过第二字线电压读取多个存储器单元以获得第二数量的第一逻辑状态，第二字线电压不同于第一字线电压; 并且如果第一逻辑状态的第一数目等于第一逻辑状态的第二数量，则使用第二字线电压作为目标字线电压。

公开(公告)号：US08045403B2

公开(公告)日：2011-10-25

申请号：US12943443

申请日：2010-11-10

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho

IPC分类号： G11C7/00

CPC分类号： G11C16/3404 ,  G11C16/3454

摘要： A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.

摘要翻译： 提供了一种应用于存储器的编程方法。 存储器包括多个存储单元。 该方法包括以下步骤。 响应于第一编程命令对存储器单元的目标单元进行编程。 响应于第二编程命令对目标单元进行编程。

公开(公告)号：US07649772B2

公开(公告)日：2010-01-19

申请号：US11779951

申请日：2007-07-19

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.

摘要翻译： 一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。 首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。 接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

公开(公告)号：US06563735B1

公开(公告)日：2003-05-13

申请号：US10117148

申请日：2002-04-04

申请人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

发明人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

IPC分类号： G11C1604

CPC分类号： G11C16/0491

摘要： A NOR-structured semiconductor memory device with a novel configuration of bit line connection is disclosed. The NOR-structured semiconductor memory device comprises a semiconductor memory cell array electrically connected to a plurality of bit lines. The plurality of bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main bit line through at least two bit line transistors, respectively. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively. During a programming or data reading operation, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage or sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device successfully prevents the programming disturbance or correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.

摘要翻译： 公开了具有位线连接的新颖结构的NOR结构的半导体存储器件。 NOR结构的半导体存储器件包括电连接到多个位线的半导体存储单元阵列。 多个位线被分成至少四个位线组。 每个位线组的至少两个位线分别通过至少两个位线晶体管耦合到主位线。 此外，NOR结构半导体存储器件的位线被布置成使得其中至少四个相邻的位线分别从四个不同的位线组中选择并且分别耦合到四个不同的主位线。 在编程或数据读取操作期间，四个相邻位线中的两个相邻位线被提供有编程电压或感测电流，而另外两个相邻位线接地。 因此，由于没有形成泄漏电流路径，所以NOR结构的半导体存储器件成功地防止了编程干扰或者以高速正确地确定存储在存储单元中的数据。

公开(公告)号：US20140075265A1

公开(公告)日：2014-03-13

申请号：US13612433

申请日：2012-09-12

申请人： Chun-Hsiung Hung ,  Hsin Yi Ho

发明人： Chun-Hsiung Hung ,  Hsin Yi Ho

IPC分类号： H03M13/05

CPC分类号： G06F11/1084 ,  G06F11/1048 ,  G11C16/349 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

摘要： The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device about the use of the ECCs. The method provides the ECC information on an output port of the device in response to a command received on an input port from a process external to the memory device. The present invention also provides a method of controlling a memory device. The method includes sending a command to the memory device requesting ECC information corresponding to data in the memory device, and receiving the ECC information from the memory device in response to the command. The method includes performing a memory management function using the ECC information.

摘要翻译： 本发明提供了一种操作存储装置的方法，该存储装置存储用于相应数据的纠错码ECC，并且包括ECC逻辑以使用ECC来校正错误。 该方法包括使用用于存储器设备上的数据的ECC来校正数据，以及在存储器设备上产生关于使用ECC的信息。 该方法响应于从存储设备外部的进程在输入端口上接收到的命令来向设备的输出端口提供ECC信息。 本发明还提供一种控制存储器件的方法。 该方法包括向存储器件发送请求与存储器件中的数据相对应的ECC信息的命令，以及响应该命令从存储器件接收ECC信息。 该方法包括使用ECC信息执行存储器管理功能。

公开(公告)号：US20110085378A1

公开(公告)日：2011-04-14

申请号：US12576323

申请日：2009-10-09

申请人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

发明人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/349

摘要： In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.

摘要翻译： 在包括多个存储单元的存储器的操作方法中，通过施加参考电压对存储器单元执行第一读取; 如果检查到第一读取结果不正确，则移动参考电压; 通过施加移动的参考电压对存储器单元执行第二读取; 如果检查到第二读取结果不正确，则将第一读取中的第一逻辑状态的第一总数与第二读取中的第一逻辑状态的第二总数进行比较; 并且如果第一读取结果具有与第二读取结果相同数量的第一逻辑状态，并且移动的参考电压被存储为目标参考电压，则参考电压的移动停止。

公开(公告)号：US20110055670A1

公开(公告)日：2011-03-03

申请号：US12943443

申请日：2010-11-10

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho

IPC分类号： G11C11/40 ,  G11C7/00 ,  G06F11/07

CPC分类号： G11C16/3404 ,  G11C16/3454

摘要： A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.

摘要翻译： 提供了一种应用于存储器的编程方法。 存储器包括多个存储单元。 该方法包括以下步骤。 响应于第一编程命令对存储器单元的目标单元进行编程。 响应于第二编程命令对目标单元进行编程。