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公开(公告)号：US07542820B2
公开(公告)日：2009-06-02
申请号：US11536582
申请日：2006-09-28
IPC分类号： G06F19/00
CPC分类号： G06N5/022 , G05B2219/32097 , G05B2219/45031
摘要： A method for affecting a creation of a recipe for processing a substrate in a processing system. The method includes providing a best-known method driven recipe editor. The best-known method driven recipe editor incorporates best-known methods (BKMs), which are best practice specifications for the recipe. The method also includes creating a plurality of BKM modules based on the BKMs for the recipe. The method further includes defining rules for parameters in the plurality of BKM modules. The rules are propagated by the BKMs. The methods moreover includes creating a BKM driven recipe by employing the best-known method driven recipe editor to enter values for the parameters within the guidelines of BKM rules.
摘要翻译： 一种用于影响在处理系统中处理衬底的配方的创建的方法。 该方法包括提供最着名的方法驱动的食谱编辑器。 最着名的方法驱动的食谱编辑器包含最着名的方法（BKM），这是方法的最佳实践规范。 该方法还包括基于用于配方的BKM创建多个BKM模块。 该方法还包括为多个BKM模块中的参数定义规则。 规则由BKM传播。 方法还包括通过采用最着名的方法驱动的配方编辑器来创建BKM驱动的配方，以便在BKM规则的指导下输入参数的值。
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公开(公告)号：US20080188970A1
公开(公告)日：2008-08-07
申请号：US11536582
申请日：2006-09-28
IPC分类号： G06F19/00
CPC分类号： G06N5/022 , G05B2219/32097 , G05B2219/45031
摘要： A method for affecting a creation of a recipe for processing a substrate in a processing system is provided. The method includes providing a best-know method driven recipe editor. The best-known method driven recipe editor incorporates best-known methods (BKMs), which are best practice specifications for the recipe. The method also includes creating a plurality of BKM modules based on the BKMs for the recipe. The method further includes defining rules for parameters in the plurality of BKM modules. The rules are propagated by the BKMs. The methods moreover includes creating a BKM driven recipe by employing the best-known method driven recipe editor to enter values for the parameters within the guidelines of BKM rules.
摘要翻译： 提供了一种用于影响在处理系统中处理衬底的配方的创建的方法。 该方法包括提供最知名的方法驱动的食谱编辑器。 最着名的方法驱动的食谱编辑器包含最着名的方法（BKM），这是方法的最佳实践规范。 该方法还包括基于用于配方的BKM创建多个BKM模块。 该方法还包括为多个BKM模块中的参数定义规则。 规则由BKM传播。 方法还包括通过采用最着名的方法驱动的配方编辑器来创建BKM驱动的配方，以便在BKM规则的指导下输入参数的值。
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公开(公告)号：US07899627B2
公开(公告)日：2011-03-01
申请号：US11536577
申请日：2006-09-28
申请人： Chung-Ho Huang , Jackie Seto , Nicolas Bright
发明人： Chung-Ho Huang , Jackie Seto , Nicolas Bright
CPC分类号： H01J37/3299 , H01J37/32935
摘要： In a plasma processing system, a method for dynamically establishing a baseline is provided. The method includes processing a first substrate. The method also includes collecting a first signal data for the first substrate. The method further includes comparing the first signal data against the baseline. The method moreover includes including the first signal data in a recalculation of the baseline if the first signal data is within a confidence level range, which is in between a top level above the baseline and a bottom level below the baseline.
摘要翻译： 在等离子体处理系统中，提供了用于动态建立基线的方法。 该方法包括处理第一衬底。 该方法还包括收集第一基底的第一信号数据。 该方法还包括将第一信号数据与基线进行比较。 该方法还包括如果第一信号数据在置信水平范围内的第一信号数据重新计算基线，其置于高于基线的最高水平和低于基线的底部水平之间。
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公开(公告)号：US20080079918A1
公开(公告)日：2008-04-03
申请号：US11536577
申请日：2006-09-28
申请人： Chung-Ho Huang , Jackie Seto , Nicolas Bright
发明人： Chung-Ho Huang , Jackie Seto , Nicolas Bright
IPC分类号： G03B27/42
CPC分类号： H01J37/3299 , H01J37/32935
摘要： In a plasma processing system, a method for dynamically establishing a baseline is provided. The method includes processing a first substrate. The method also includes collecting a first signal data for the first substrate. The method further includes comparing the first signal data against the baseline. The method moreover includes including the first signal data in a recalculation of the baseline if the first signal data is within a confidence level range, which is in between a top level above the baseline and a bottom level below the baseline.
摘要翻译： 在等离子体处理系统中，提供了用于动态建立基线的方法。 该方法包括处理第一衬底。 该方法还包括收集第一基底的第一信号数据。 该方法还包括将第一信号数据与基线进行比较。 该方法还包括如果第一信号数据在置信水平范围内的第一信号数据重新计算基线，其置于高于基线的最高水平和低于基线的底部水平之间。
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5.发明申请PROCESS INTEGRATION SCHEME TO LOWER OVERALL DIELECTRIC CONSTANT IN BEOL INTERCONNECT STRUCTURES 审中-公开过程集成方案降低BEOL互连结构中的总体电介质常数公开(公告)号：US20090134520A1
公开(公告)日：2009-05-28
申请号：US12366235
申请日：2009-02-05
申请人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
发明人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
IPC分类号： H01L23/52
CPC分类号： H01L21/76822 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
摘要翻译： 提供了后端（BEoL）互连结构及其制造方法。 这些结构的特征在于导线越窄，总体介电常数值越小。 保形扩散阻挡层和选择性形成的覆盖层用于将导线和通孔与互连结构中的周围电介质层隔离。 本发明的方法采用技术来缩小光致抗蚀剂掩模中的开口，以便限定更窄的通孔。 更窄的通孔增加了通孔和导电线之间可以容许的不对准量。
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公开(公告)号：US07465525B2
公开(公告)日：2008-12-16
申请号：US11126466
申请日：2005-05-10
申请人： S. M. Reza Sadjadi , Nicolas Bright
发明人： S. M. Reza Sadjadi , Nicolas Bright
IPC分类号： G03F9/00
CPC分类号： H01L21/0338 , G03F7/70433 , G03F7/70466
摘要： A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.
摘要翻译： 提供了一种用于产生多个标线布局的方法。 接收具有特征布局间距的特征布局。 从特征布局生成多个标线布局，其中多个标线布局的每个标线布局具有标线布局间距，并且其中每个标线布局间距至少是特征布局间距的两倍。
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7.发明授权Apparatus methods for controlling wafer temperature in chemical mechanical polishing 失效用于控制化学机械抛光中晶片温度的装置方法公开(公告)号：US06984162B2
公开(公告)日：2006-01-10
申请号：US10722839
申请日：2003-11-25
申请人： Nicolas Bright , David J. Hemker
发明人： Nicolas Bright , David J. Hemker
IPC分类号： B24B1/00
CPC分类号： B24B37/015 , B24B37/30
摘要： Apparatus controls the temperature of a wafer for chemical mechanical polishing operations. A wafer carrier wafer mounting surface positions a wafer adjacent to a thermal energy transfer unit for transferring energy relative to the wafer. A thermal energy detector oriented adjacent to the wafer mounting surface detects the temperature of the wafer. A controller is responsive to the detector for controlling the supply of thermal energy relative to the thermal energy transfer unit. Embodiments include defining separate areas of the wafer, providing separate sections of the thermal energy transfer unit for each separate area, and separately detecting the temperature of each separate area to separately control the supply of thermal energy relative to the thermal energy transfer unit associated with the separate area.
摘要翻译： 设备控制用于化学机械抛光操作的晶片的温度。 晶片载体晶片安装表面将晶片邻近热能传递单元定位，以相对于晶片转移能量。 定位成与晶片安装表面相邻的热能检测器检测晶片的温度。 控制器响应于检测器来控制相对于热能传递单元的热能供应。 实施例包括限定晶片的分开的区域，为每个单独的区域提供热能传递单元的分开的部分，并且单独地检测每个分离区域的温度，以单独地控制相对于与所述热能传递单元相关联的热能传递单元的热能供应 分开区域。
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8.发明申请Process integration scheme to lower overall dielectric constant in BEoL interconnect structures 有权过程集成方案，以降低BEoL互连结构中的总体介电常数公开(公告)号：US20080150138A1
公开(公告)日：2008-06-26
申请号：US11732198
申请日：2007-04-02
申请人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
发明人： Nicolas Bright , David Hemker , Fritz C. Redeker , Yezdi Dordi
IPC分类号： H01L21/4763 , H01L23/52
CPC分类号： H01L21/76822 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
摘要翻译： 提供了后端（BEoL）互连结构及其制造方法。 这些结构的特征在于导线越窄，总介电常数值越小。 保形扩散阻挡层和选择性形成的覆盖层用于将导线和通孔与互连结构中的周围电介质层隔离。 本发明的方法采用技术来缩小光致抗蚀剂掩模中的开口，以便限定更窄的通孔。 更窄的通孔增加了通孔和导电线之间可以容许的不对准量。
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9.发明授权Smart component-based management techniques in a substrate processing system 有权基于基于组件的管理技术在基板处理系统中的应用公开(公告)号：US07152011B2
公开(公告)日：2006-12-19
申请号：US10927161
申请日：2004-08-25
IPC分类号： G06F19/00
CPC分类号： G01R31/3187 , G05B19/4184 , G05B2219/31362 , G05B2219/31463 , Y02P90/14 , Y02P90/86
摘要： A method of component management in a substrate processing system is disclosed. The substrate processing system has a set of components, at least a plurality of components of the set of components being designated to be smart components, each component of the plurality of components having an intelligent component enhancement (ICE). The method includes querying the plurality of components to request their respective unique identification data from their respective ICEs. The method further includes receiving unique identification data from the plurality of components if any of the plurality of components responds to the querying. The method additionally includes flagging the first component for corrective action if a first component of the plurality of components fails to provide first component unique identification data when the first component identification data is expected.
摘要翻译： 公开了一种基板处理系统中的部件管理方法。 衬底处理系统具有一组组件，该组组件中的至少多个组件被指定为智能组件，多个组件的每个组件具有智能组件增强（ICE）。 该方法包括查询多个组件以从它们各自的ICE请求它们各自的唯一标识数据。 该方法还包括如果多个组件中的任何组件响应于查询，则从多个组件接收唯一的标识数据。 该方法另外包括：如果在预期第一组件识别数据时多个组件的第一组件不能提供第一组件唯一标识数据，则标记第一组件以用于校正动作。
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公开(公告)号：US20060259886A1
公开(公告)日：2006-11-16
申请号：US11126708
申请日：2005-05-10
申请人： S.M. Sadjadi , Nicolas Bright
发明人： S.M. Sadjadi , Nicolas Bright
CPC分类号： G03F1/36
摘要： An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and length, shape modifications, etc. for forming features in a patterned layer.
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