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    Reticle alignment and overlay for multiple reticle process
    1.
    发明申请
    Reticle alignment and overlay for multiple reticle process 有权
    掩模版校准和覆盖多个标线工艺

    公开(公告)号：US20060257750A1

    公开(公告)日：2006-11-16

    申请号：US11126466

    申请日：2005-05-10

    申请人： S.M. Sadjadi ,  Nicolas Bright

    发明人： S.M. Sadjadi ,  Nicolas Bright

    IPC分类号： G03F1/00 ,  G03F9/00 ,  G03C5/00

    CPC分类号： H01L21/0338 ,  G03F7/70433 ,  G03F7/70466

    摘要： A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.

    摘要翻译： 提供了一种用于产生多个标线布局的方法。 接收具有特征布局间距的特征布局。 从特征布局生成多个标线布局，其中多个标线布局的每个标线布局具有标线布局间距，并且其中每个标线布局间距至少是特征布局间距的两倍。

    Computer readable mask shrink control processor
    2.
    发明申请
    Computer readable mask shrink control processor 有权

    公开(公告)号：US20060259886A1

    公开(公告)日：2006-11-16

    申请号：US11126708

    申请日：2005-05-10

    申请人： S.M. Sadjadi ,  Nicolas Bright

    发明人： S.M. Sadjadi ,  Nicolas Bright

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00

    CPC分类号： G03F1/36

    摘要： An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and length, shape modifications, etc. for forming features in a patterned layer.

    Pitch reduction
    3.
    发明申请
    Pitch reduction 有权
    节距减少

    公开(公告)号：US20070264830A1

    公开(公告)日：2007-11-15

    申请号：US11432194

    申请日：2006-05-10

    申请人： Zhisong Huang ,  Jeffrey Marks ,  S.M. Sadjadi

    发明人： Zhisong Huang ,  Jeffrey Marks ,  S.M. Sadjadi

    IPC分类号： H01L21/311 ,  H01L21/306

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

    摘要： A method for providing features in an etch layer is provided. A sacrificial patterned layer with sacrificial features is provided over an etch layer. Conformal sidewalls are formed in the sacrificial features, comprising at least two cycles of a sidewall formation process, wherein each cycle comprises a sidewall deposition phase and a sidewall profile shaping phase. Parts of the sacrificial patterned layer between conformal sidewalls are removed leaving the conformal sidewalls with gaps between the conformal sidewalls where parts of the sacrificial patterned layer were selectively removed. Features are etched in the etch layer using the conformal sidewalls as an etch mask, wherein the features in the etch layer are etched through the gaps between the conformal sidewalls where parts of the sacrificial patterned layer were selectively removed.

    摘要翻译： 提供了一种用于在蚀刻层中提供特征的方法。 在蚀刻层上提供具有牺牲特征的牺牲图案层。 保形侧壁形成在牺牲特征中，包括侧壁形成工艺的至少两个循环，其中每个循环包括侧壁沉积阶段和侧壁轮廓成形阶段。 除去共形侧壁之间的牺牲图案层的部分，留下保形侧壁，其中保形侧壁之间的间隙被选择性地去除牺牲图案层的部分。 使用保形侧壁作为蚀刻掩模在蚀刻层中蚀刻特征，其中蚀刻层中的特征被蚀刻通过牺牲图案层的部分被选择性去除的共形侧壁之间的间隙。

    Fast gas switching plasma processing apparatus
    4.
    发明申请
    Fast gas switching plasma processing apparatus 审中-公开
    快速气体开关等离子体处理装置

    公开(公告)号：US20070066038A1

    公开(公告)日：2007-03-22

    申请号：US11601293

    申请日：2006-11-17

    申请人： S.M. Sadjadi ,  Zhisong Huang ,  Jose Sam ,  Eric Lenz ,  Rajinder Dhindsa

    发明人： S.M. Sadjadi ,  Zhisong Huang ,  Jose Sam ,  Eric Lenz ,  Rajinder Dhindsa

    IPC分类号： H01L21/00 ,  C23F1/00 ,  H01L21/306 ,  C23C16/00 ,  H01L21/20

    CPC分类号： H01J37/32091 ,  H01J37/32155 ,  H01J37/3244 ,  H01J37/32449

    摘要： A plasma chamber with a plasma confinement zone with an electrode is provided. A gas distribution system for providing a first gas and a second gas is connected to the plasma chamber, wherein the gas distribution system can substantially replace one gas in the plasma zone with the other gas within a period of less than 1 s. A first frequency tuned RF power source for providing power to the electrode in a first frequency range is electrically connected to the at least one electrode wherein the first frequency tuned RF power source is able to minimize a reflected RF power. A second frequency tuned RF power source for providing power to the plasma chamber in a second frequency range outside of the first frequency range wherein the second frequency tuned RF power source is able to minimize a reflected RF power.

    摘要翻译： 提供具有电极等离子体限制区的等离子体室。 用于提供第一气体和第二气体的气体分配系统连接到等离子体室，其中气体分配系统可以在小于1秒的时间内基本上替换等离子体区域中的一种气体与另一种气体。 用于在第一频率范围内向电极提供功率的第一频率调谐RF电源电连接到至少一个电极，其中第一频率调谐的RF功率源能够最小化反射的RF功率。 用于在第一频率范围之外的第二频率范围内为等离子体室提供功率的第二频率调谐RF电源，其中第二频率调谐的RF功率源能够使反射的RF功率最小化。

    Reducing line edge roughness
    5.
    发明申请
    Reducing line edge roughness 审中-公开
    减少线边缘粗糙度

    公开(公告)号：US20070181530A1

    公开(公告)日：2007-08-09

    申请号：US11350488

    申请日：2006-02-08

    申请人： Zhi-Song Huang ,  S.M. Sadjadi ,  Lumin Li ,  Conan Chiang

    发明人： Zhi-Song Huang ,  S.M. Sadjadi ,  Lumin Li ,  Conan Chiang

    IPC分类号： C23F1/00 ,  H01L21/461 ,  H01L21/302

    CPC分类号： H01L21/31144 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

    摘要： A method of forming features in an etch layer disposed below a mask with features is provided. The mask is conditioned. The conditioning, comprising providing a conditioning gas consisting essentially of at least one noble gas, forming a plasma from the conditioning gas, and exposing the mask to the plasma from the conditioning gas. The features of the mask are shrunk. Features are etched into the etch layer through the shrunk features of the mask.

    摘要翻译： 提供了一种在具有特征的掩模下方设置的蚀刻层中形成特征的方法。 面具是有条件的。 该调理装置包括提供基本上由至少一种惰性气体组成的调节气体，从调节气体形成等离子体，以及将掩模从调节气体暴露于等离子体。 面具的特征缩小。 通过掩模的收缩特征将特征蚀刻到蚀刻层中。

    Vertical profile fixing
    6.
    发明申请
    Vertical profile fixing 有权
    垂直型材固定

    公开(公告)号：US20070075038A1

    公开(公告)日：2007-04-05

    申请号：US11244870

    申请日：2005-10-05

    申请人： S.M. Sadjadi ,  Peter Cirigliano ,  Jisoo Kim ,  Zhisong Huang ,  Eric Hudson

    发明人： S.M. Sadjadi ,  Peter Cirigliano ,  Jisoo Kim ,  Zhisong Huang ,  Eric Hudson

    IPC分类号： B44C1/22 ,  C23F1/00 ,  H01L21/306 ,  C03C15/00

    CPC分类号： H01L21/0273 ,  H01L21/31144

    摘要： A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have irregular profiles along depths of the photoresist features. The irregular profiles along the depths of the photoresist features of the sidewalls of the photoresist features are corrected comprising at least one cycle, where each cycle comprises a sidewall deposition phase and a profile shaping phase. Feature is etched into the etch layer through the photoresist features. The mask is removed.

    摘要翻译： 提供了一种蚀刻蚀刻层中的特征的方法。 在具有侧壁的光致抗蚀剂特征的蚀刻层上形成图案化的光致抗蚀剂掩模，其中光致抗蚀剂特征的侧壁沿光致抗蚀剂特征的深度具有不规则的轮廓。 沿光致抗蚀剂特征的侧壁的光致抗蚀剂特征的深度的不规则轮廓被校正包括至少一个循环，其中每个循环包括侧壁沉积阶段和轮廓成形阶段。 通过光致抗蚀剂特征将特征蚀刻到蚀刻层中。 去除面具。

    Reduction of etch mask feature critical dimensions
    7.
    发明申请
    Reduction of etch mask feature critical dimensions 审中-公开
    蚀刻掩模的减少具有关键尺寸

    公开(公告)号：US20060134917A1

    公开(公告)日：2006-06-22

    申请号：US11016455

    申请日：2004-12-16

    申请人： Zhisong Huang ,  S.M. Sadjadi ,  Jeffrey Marks

    发明人： Zhisong Huang ,  S.M. Sadjadi ,  Jeffrey Marks

    IPC分类号： H01L21/4757 ,  C23F1/00

    CPC分类号： H01L21/67069 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

    摘要： A method for forming features in an etch layer in an etch stack with an etch mask over the etch layer, wherein the etch mask has etch mask features with sidewalls, where the etch mask features have a first critical dimension, is provided. A cyclical critical dimension reduction is performed to form deposition layer features with a second critical dimension, which is less than the first critical dimension. Each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including the vertical sidewalls, of the etch mask features and an etching phase for etching back the deposition layer leaving a selective deposition on the vertical sidewalls. Features are etched into the etch layer, wherein the etch layer features have a third critical dimension, which is less than the first critical dimension.

    摘要翻译： 一种用于在蚀刻层上的蚀刻层中形成蚀刻层中的特征的方法，其中蚀刻掩模具有带侧壁的蚀刻掩模特征，其中蚀刻掩模特征具有第一临界尺寸。 执行周期性临界尺寸降低以形成具有小于第一临界尺寸的第二临界尺寸的沉积层特征。 每个循环包括沉积相，用于在包括垂直侧壁的蚀刻掩模特征的暴露表面上沉积沉积层，以及用于蚀刻回沉积层的蚀刻阶段，在垂直侧壁上留下选择性沉积。 将特征蚀刻到蚀刻层中，其中蚀刻层特征具有小于第一临界尺寸的第三临界尺寸。

    Trench etch process for low-k dielectrics
    8.
    发明申请
    Trench etch process for low-k dielectrics 有权
    低k电介质的沟槽蚀刻工艺

    公开(公告)号：US20050009324A1

    公开(公告)日：2005-01-13

    申请号：US10826211

    申请日：2004-04-16

    申请人： SiYi Li ,  S.M. Sadjadi ,  David Pirkle ,  Stephan Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

    发明人： SiYi Li ,  S.M. Sadjadi ,  David Pirkle ,  Stephan Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

    IPC分类号： H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/31116 ,  H01L21/02126 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76804 ,  H01L21/76808

    摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

    摘要翻译： 本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。 在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。 在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。 优选地，该方法用于不具有中间蚀刻停止层的低k电介质。 另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。 作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

    Reduction of feature critical dimensions using multiple masks
    9.
    发明申请
    Reduction of feature critical dimensions using multiple masks 有权
    使用多个掩模降低功能关键尺寸

    公开(公告)号：US20060172540A1

    公开(公告)日：2006-08-03

    申请号：US11050985

    申请日：2005-02-03

    申请人： Jeffrey Marks ,  S.M. Sadjadi

    发明人： Jeffrey Marks ,  S.M. Sadjadi

    IPC分类号： H01L21/311

    CPC分类号： H01L21/0273 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

    摘要： A method for forming features in an etch layer is provided. A first mask is formed over the etch layer wherein the first mask defines a plurality of spaces with widths. A sidewall layer is formed over the first mask. Features are etched into the etch layer through the sidewall layer, wherein the features have widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed. An additional mask is formed over the etch layer wherein the additional mask defines a plurality of spaces with widths. A sidewall layer is formed over the additional mask. Features are etched into the etch layer through the sidewall layer, wherein the widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed.

    摘要翻译： 提供了一种在蚀刻层中形成特征的方法。 在蚀刻层上形成第一掩模，其中第一掩模限定具有宽度的多个空间。 在第一掩模上形成侧壁层。 特征通过侧壁蚀刻到蚀刻层中，其中特征具有小于由第一掩模限定的空间的宽度的宽度。 去除掩模和侧壁层。 在蚀刻层上形成另外的掩模，其中附加掩模限定具有宽度的多个空间。 侧壁层形成在附加掩模上。 特征通过侧壁蚀刻到蚀刻层中，其中宽度小于由第一掩模限定的空间的宽度。 去除掩模和侧壁层。