公开(公告)号：US20060113627A1

公开(公告)日：2006-06-01

申请号：US10999508

申请日：2004-11-29

申请人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Chang

发明人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Chang

IPC分类号： H01L29/00

CPC分类号： H01L29/7835 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

摘要翻译： 提供了一种用于后续接触孔工艺的具有层间电介质（ILD）蚀刻停止层的高压晶体管器件。 蚀刻停止层是具有大于10欧姆 - 厘米电阻率的高电阻率薄膜，因此在栅极处驱动大于5V的高电压时，可以防止泄漏并提高击穿电压。 制造高压器件的方法与当前的低压器件工艺和中压器件工艺兼容。

公开(公告)号：US07301185B2

公开(公告)日：2007-11-27

申请号：US10999508

申请日：2004-11-29

申请人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Xiu Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Cheng

发明人： Chung-I Chen ,  Hsin Kuan ,  Zhi-Cheng Chen ,  Rann-Shyan Yeh ,  Chi-Hsuen Chang ,  Jun Xiu Liu ,  Tzu-Chiang Sung ,  Chia-Wei Liu ,  Jieh-Ting Cheng

IPC分类号： H01L27/148 ,  H01L29/80 ,  H01L21/824

CPC分类号： H01L29/7835 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

摘要翻译： 提供了一种用于后续接触孔工艺的具有层间电介质（ILD）蚀刻停止层的高压晶体管器件。 蚀刻停止层是具有大于10欧姆 - 厘米电阻率的高电阻率薄膜，因此在栅极处驱动大于5V的高电压时，可以防止泄漏并提高击穿电压。 制造高压器件的方法与当前的低压器件工艺和中压器件工艺兼容。

公开(公告)号：US20070235831A1

公开(公告)日：2007-10-11

申请号：US11273228

申请日：2005-11-12

申请人： Chia-Wei Liu ,  Jun Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

发明人： Chia-Wei Liu ,  Jun Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/088

摘要： A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

摘要翻译： 用于隔离各种工作电压的第一电路和第二电路的半导体结构包括围绕半导体衬底上的第一和第二电路的第一隔离环。 在第一和第二电路下连续延伸的掩埋层形成在半导体衬底上，其中掩埋层与第一隔离环接合，用于将第一和第二电路与半导体衬底的背面偏置隔离。 离子增强隔离层介于掩埋层和形成有第一和第二电路的器件的阱区之间，其中离子增强隔离层掺杂了与掩埋层不同的极性类型的杂质。

公开(公告)号：US07498653B2

公开(公告)日：2009-03-03

申请号：US11273228

申请日：2005-11-12

申请人： Chia-Wei Liu ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

发明人： Chia-Wei Liu ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

IPC分类号： H01L29/00

CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/088

摘要： A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

摘要翻译： 用于隔离各种工作电压的第一电路和第二电路的半导体结构包括围绕半导体衬底上的第一和第二电路的第一隔离环。 在第一和第二电路下连续延伸的掩埋层形成在半导体衬底上，其中掩埋层与第一隔离环接合，用于将第一和第二电路与半导体衬底的背面偏置隔离。 离子增强隔离层介于掩埋层和形成有第一和第二电路的器件的阱区之间，其中离子增强隔离层掺杂了与掩埋层不同的极性类型的杂质。