公开(公告)号：US06372645B1

公开(公告)日：2002-04-16

申请号：US09439367

申请日：1999-11-15

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu ,  Shih-Chi Lin ,  Ming-Jer Lee ,  Ying-Lang Wang ,  Yu-Ku Lin

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu ,  Shih-Chi Lin ,  Ming-Jer Lee ,  Ying-Lang Wang ,  Yu-Ku Lin

IPC分类号： H01L2144

CPC分类号： H01L21/76838 ,  H01L21/32051

摘要： In the first option of the present invention, a semiconductor structure is provided and an overlying titanium nitride barrier layer is deposited thereon at about 100° C. At least Al and Cu is sputtered over the titanium nitride barrier layer from about 270 to 300° C. to form an Al—Cu alloy containing metal layer. The sputtered Al—Cu alloy containing metal layer is promptly cooled at a cooling rate greater than about 100° C./minute to a temperature below 200° C. to form a Al—Cu alloy containing metal layer having minimal CuAl2 grain growth. The semiconductor structure is removed from the cooling chamber and the semiconductor structure is processed further below 200° C. to form semiconductor device precursors. In the second option of the present invention, a semiconductor structure having an overlying barrier layer is provided. At least Al and Cu is sputtered over the barrier layer at a first temperature to form an Al—Cu alloy containing metal layer having CuAl2 grains of a first average size. The semiconductor structure is processed and then heated to a second temperature to dissolve the CuAl2 grains of a first average size then rapidly cooling to a third temperature whereby the CuAl2 grains formed have a second average size within the Al—Cu alloy containing metal layer. The second average size CuAl2 grains being less than the first average size CuAl2 grains.

摘要翻译： 在本发明的第一种选择中，提供了一种半导体结构，并在其上沉积了大约100℃的上覆氮化钛阻挡层。至少Al和Cu溅射在氮化钛阻挡层上约270-300℃ 以形成含有金属层的Al-Cu合金。 将溅射的含有Al-Cu合金的金属层以大于约100℃/分钟的冷却速度迅速冷却到低于200℃的温度，以形成含有最小CuAl 2晶粒生长的金属层的Al-Cu合金。 将半导体结构从冷却室中移除，半导体结构进一步在200℃以下进行处理以形成半导体器件前体。 在本发明的第二个选择中，提供了具有上覆阻挡层的半导体结构。 在第一温度下至少将Al和Cu溅射在阻挡层上，以形成含有具有第一平均尺寸的CuAl 2晶粒的金属层的Al-Cu合金。 将半导体结构加工，然后加热至第二温度以溶解第一平均尺寸的CuAl 2晶粒，然后快速冷却至第三温度，由此形成的CuAl 2晶粒在含有Al-Cu合金的金属层内具有第二平均尺寸。 第二平均尺寸CuAl2晶粒小于第一平均尺寸CuAl2晶粒。

公开(公告)号：US06242338B1

公开(公告)日：2001-06-05

申请号：US09422175

申请日：1999-10-22

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

IPC分类号： H01L214763

CPC分类号： H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31629 ,  H01L21/321 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888

摘要： A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

摘要翻译： 已经开发了在沉积含卤素的低k电介质层之前在金属互连结构的侧面上形成薄的保护性绝缘体层的工艺。 该方法的特征在于金属互连结构的暴露侧上通过等离子体处理在含氮或含水环境中进行的金属氮化物或薄金属氧化物层的生长。 薄层保护金属互连结构免受由覆盖在低k电介质层（例如氟化石英玻璃）中的卤素或卤素产物产生的腐蚀性以及分层影响。

公开(公告)号：US06297158B1

公开(公告)日：2001-10-02

申请号：US09583402

申请日：2000-05-31

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76864

摘要： In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure. Finally, the interconnect so formed by either of the embodiments is subjected to CMP. It is found that, through the disclosed method of treatment of the barrier layer, process stresses that are normally formed within the barrier layer are relieved, and hence no damage is incurred during the final steps of chemical-mechanical polishing.

摘要翻译： 在本公开的发明中，提供了一种方法，以避免对互连线进行化学机械抛光（CMP）的铜互连的损坏。 首先，在大马士革结构中形成铜阻挡层。 然后，在将铜金属沉积到镶嵌开口之前，在镶嵌结构的内壁上形成阻挡层。 在第一实施例中，铜阻挡层在高温下沉积。 然后，以规定的方式冷却。 随后，在屏障上形成铜籽晶层，随后是铜的电化学沉积（ECD），以形成铜镶嵌互连。 或者，在第二实施例中，铜层在低温下形成。 然后在高温下进行退火，然后进行晶片冷却。 随后，在阻挡层上形成铜籽晶层。 接下来，在镶嵌结构中形成ECD铜。 最后，将由这两个实施例形成的互连件进行CMP处理。 发现通过公开的阻挡层处理方法，通常在阻挡层内形成的工艺应力被释放，因此在化学机械抛光的最终步骤期间不会产生损伤。

公开(公告)号：US06221758B1

公开(公告)日：2001-04-24

申请号：US09225064

申请日：1999-01-04

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76856 ,  H01L21/76805 ,  H01L21/76843

摘要： In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

公开(公告)号：US06207568B1

公开(公告)日：2001-03-27

申请号：US09200554

申请日：1998-11-27

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/76841 ,  H01L21/2855 ,  H01L21/28568 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.

摘要翻译： 一种形成含铝导体层的方法。 首先提供基板。 然后在衬底上形成采用电离金属等离子体偏置溅射方法的钛层。 最后，在钛层上形成含有铝的导体层。 通过采用用于形成钛层的电离金属等离子体偏压溅射法，形成具有增强（111）晶体取向的含铝导体层。 该方法对于形成具有增强的电迁移电阻的含铝导体层特别有用，即使在钛层和含铝导体层之间形成氮化钛层的情况下也是如此。

公开(公告)号：US06353260B2

公开(公告)日：2002-03-05

申请号：US09785106

申请日：2001-02-20

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2348

CPC分类号： H01L21/76856 ,  H01L21/76805 ,  H01L21/76843

摘要： In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

摘要翻译： 在通过以下步骤形成其中导电基板被电介质层覆盖的半导体器件中，在电介质层的顶部形成有沟槽线的沟槽和底部的接触孔，其中整个沟槽到达 基质。 清洁沟槽。 在包括沟槽壁的电介质层上形成钽膜，覆盖暴露的衬底表面。 用钽氧化物和氮化钽中的至少一种填充钽膜的晶界，形成填充的钽膜。 在填充的钽膜上方形成再沉积的钽层。 在再沉积的钽膜上方形成铜籽晶膜。 将装有填充沟槽的装置用种子膜上的电镀体铜层铺平。 平面化器件以暴露电介质层的顶表面，去除填充的钽膜，铜籽晶膜和块状铜层的剩余部分。 填充的钽膜通过在STP大气条件下暴露于空气或通过在约400℃的温度下暴露于等离子体中的一氧化二氮（N 2 O）气体而形成。

公开(公告)号：US06277745B1

公开(公告)日：2001-08-21

申请号：US09221965

申请日：1998-12-28

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/02071 ,  H01L21/321 ,  H01L21/32136 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885

摘要： The present invention relates to a new structure and method for the passivation of copper electrical interconnects for the semiconductor industry. More particularly, the invention details a convenient method for completing the passivation of copper lines after they have been patterned by a dry etch process. The method includes the formation of a sandwich structure consisting of a bottom barrier layer, a copper layer and a top barrier layer. After the sandwich structure is patterned with a dry etch, for example, the resultant exposed copper sidewalls are then passivated by means of a barrier metal spacer process. The fully encapsulated copper lines are highly resistant to oxidation, which is an, otherwise, inherent problem associated with the lack of self passivation/exhibited by bare copper films.

摘要翻译： 本发明涉及用于半导体工业的铜电互连钝化的新结构和方法。 更具体地，本发明详细描述了在通过干蚀刻工艺对其进行图案化之后完成铜线钝化的方便方法。 该方法包括形成由底部阻挡层，铜层和顶部阻挡层组成的夹层结构。 在用干蚀刻图案化夹层结构之后，然后通过阻挡金属间隔物工艺钝化所得到的暴露的铜侧壁。 完全封装的铜线具有很高的抗氧化性，这是另一种与裸铜膜缺乏自钝化/显示相关的固有问题。

公开(公告)号：US06177347B1

公开(公告)日：2001-01-23

申请号：US09346527

申请日：1999-07-02

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/76814 ,  H01L21/76808 ,  H01L21/76843

摘要： A new method of in-situ cleaning in a copper metallization process is described. A copper line is provided overlying a first insulating layer on a semiconductor substrate. A silicon nitride layer is deposited overlying the copper line. A second insulating layer is deposited overlying the silicon nitride layer. A via is opened through the second insulating layer to the silicon nitride layer wherein a polymer forms on the sidewalls of the via. The silicon nitride layer within the via is removed wherein the copper line underlying the silicon nitride layer is exposed within the via and whereby the exposed copper line is oxidized forming a copper oxide layer within the via. The via is cleaned within a deposition chamber wherein the cleaning comprises the following steps: first sputtering Argon into the via to remove the polymer, second pumping down the deposition chamber, and third flowing H2 and He gases into the via to reduce the copper oxide layer to copper. Thereafter, a barrier metal layer is deposited onto the third insulating layer and within the via using the same deposition chamber and maintaining vacuum. A copper layer is formed within the via overlying the barrier metal layer to complete the copper metallization in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种在铜金属化过程中原位清洗的新方法。 铜线设置在半导体衬底上的第一绝缘层上。 沉积在铜线上的氮化硅层。 沉积在氮化硅层上的第二绝缘层。 将通孔穿过第二绝缘层打开到氮化硅层，其中在通孔的侧壁上形成聚合物。 去除通孔内的氮化硅层，其中氮化硅层下面的铜线在通孔内暴露，由此暴露的铜线被氧化，形成通孔内的氧化铜层。 在沉积室中清洁通孔，其中清洁包括以下步骤：首先将氩气溅射到通孔中以除去聚合物，第二次将沉积室泵送，并且将第三流动的H 2和He气体进入通孔以减少氧化铜层 到铜。 此后，使用相同的沉积室将阻挡金属层沉积到第三绝缘层和通孔内，并保持真空。 在覆盖阻挡金属层的通孔中形成铜层，以在集成电路器件的制造中完成铜金属化。

公开(公告)号：US06544882B1

公开(公告)日：2003-04-08

申请号：US09482049

申请日：2000-01-13

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21302

CPC分类号： H01L21/7685 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/31629 ,  H01L21/76858 ,  Y10S438/952

摘要： In the fabrication of integrated circuits containing multilevel structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers, superior adhesion between the FSG and aluminum-copper-TiN is achieved by subjecting the aluminum-copper-TiN layer to a plasma containing N2 and H2 or N2 and NH3 prior to deposition of the FSG layer. It is believed that the plasma treatment converts unreacted Ti within the TiN layer to TiN and, also, stuffs grain boundaries within the TiN layer with N2. The result is a void-free TiN layer which is impervious to F atoms residing in the FSG layer.

摘要翻译： 在包含FSG（F掺杂SiO 2）电介质层和铝 - 铜-TiN层的多层结构的集成电路的制造中，FSG和铝 - 铜-TiN层之间的优异的附着力通过将铝 - 铜-TiN层 在沉积FSG层之前，含有N 2和H 2或N 2和NH 3的等离子体。 据信等离子体处理将TiN层内的未反应的Ti转化为TiN，并且还用N 2将TiN层内的晶界填充。 结果是无孔的TiN层，其不存在存在于FSG层中的F原子。

公开(公告)号：US06500749B1

公开(公告)日：2002-12-31

申请号：US09810123

申请日：2001-03-19

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to fabricate a metal via structure having improved electromigration resistance, comprising the following steps. A semiconductor structure having an exposed metal interconnect structure therein is provided. The metal interconnect structure including a metal via portion. A capping layer is formed over the metal interconnect structure. A via pattern structure is formed over the capping layer. The via pattern structure having a via pattern hole aligned with the metal via portion of the metal interconnect structure. Ions are implanted through the via pattern hole into the metal via portion, and any portion of the metal interconnect structure above the metal via portion. Whereby the metal via portion and the portion of the metal interconnect structure above the metal via portion have improved electromigration resistance.

摘要翻译： 一种制造具有改善的电迁移阻力的金属孔结构的方法，包括以下步骤。 提供其中具有暴露的金属互连结构的半导体结构。 金属互连结构包括金属通孔部分。 在金属互连结构上形成覆盖层。 在覆盖层上形成通孔图案结构。 通孔图案结构具有与金属互连结构的金属通孔部分对准的通孔图形孔。 离子通过通孔图案孔注入金属通孔部分中，并且金属互连结构的任何部分在金属通孔部分上方。 金属通孔部分和金属通孔部分上方的金属互连结构的部分具有改善的电迁移阻力。