公开(公告)号：US12039090B2

公开(公告)日：2024-07-16

申请号：US17394014

申请日：2021-08-04

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Michael Chandler-Page ,  Pradeep Saminathan ,  Jon Eklund ,  Neil Whyte ,  José Arnaldo Bianco Filho ,  Abhinav Sharma

IPC: G06F12/14 ,  G06F9/4401 ,  G06F13/16 ,  G06F21/71 ,  G06F21/60 ,  G06F21/62 ,  G06F21/74 ,  G06F21/76 ,  G06F21/85

CPC classification number: G06F21/71 ,  G06F9/4406 ,  G06F12/1441 ,  G06F13/1663 ,  G06F21/76 ,  G06F2212/1052

Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.

公开(公告)号：US11809334B2

公开(公告)日：2023-11-07

申请号：US17232514

申请日：2021-04-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil Whyte ,  Michael Chandler-Page ,  Pradeep Saminathan ,  Jon Eklund

IPC: G06F12/14 ,  G06F3/16 ,  G06F9/4401 ,  G06F21/60 ,  G06F21/62 ,  G06F21/74 ,  G06F21/85 ,  G06F21/76 ,  G06F13/16

CPC classification number: G06F12/1441 ,  G06F13/1668 ,  G06F2212/1052

Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.

公开(公告)号：US11567848B2

公开(公告)日：2023-01-31

申请号：US17106324

申请日：2020-11-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil Whyte ,  Andy Brewster ,  Jens Puchert

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/07 ,  G06F11/16 ,  G06F13/24 ,  G06F13/42

Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.

公开(公告)号：US11455002B1

公开(公告)日：2022-09-27

申请号：US17331967

申请日：2021-05-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Neil Whyte ,  Andy Brewster ,  Angus Black

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10

Abstract: A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.