-
公开(公告)号：US20210075404A1
公开(公告)日：2021-03-11
申请号：US17086728
申请日：2020-11-02
发明人： Gary ROBERTSON , Hamed SADATI , Rupesh KHARE , Sameer BAVEJA
摘要： This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (114P) is enabled by a reset condition (RST) for the audio driving circuit.
-
公开(公告)号：US20240204734A1
公开(公告)日：2024-06-20
申请号：US18476962
申请日：2023-09-28
IPC分类号： H03F1/52
CPC分类号： H03F1/523 , H03F3/45071 , H03F2200/441
摘要： Circuitry for driving first and second loads, the circuitry comprising: a first output signal path for supplying a first driving signal to the first load; a second output signal path for supplying a second driving signal to the second load; sequencer circuitry configured to initiate a first state change in the first output signal path and a second state change in the second output signal path, wherein the sequencer circuitry is configured to control the initiation of the first and second state changes such that the second state change is not synchronised with the first state change.
-
公开(公告)号：US20220404407A1
公开(公告)日：2022-12-22
申请号：US17354237
申请日：2021-06-22
发明人： Mehul MISTRY , Rupesh KHARE , Jack FULLER
摘要： Circuitry for detecting a capacitive load coupled between a first node and a second node, the circuitry comprising: drive circuitry for applying a first voltage to a first node over a first time period; processing circuitry configured to: measure a second voltage at the first node; and determine that the load is a capacitive load based on the second voltage.
-
公开(公告)号：US20200186918A1
公开(公告)日：2020-06-11
申请号：US16708854
申请日：2019-12-10
发明人： Rupesh KHARE , Simon FOSTER
摘要： This application relates to switch arrangements, in particular switch arrangements suitable for switchable connecting nodes of audio driving circuitry (100) that may, in use, experience a signal swing depending on an output audio driving signal (VD). A switch arrangement (300) comprises first and second transistors (301 and 302) of the same polarity type connected in series between the first and second nodes, with a third transistor (303) connected between a defined voltage (VS) and an intermediate node (N3) between the first and second transistors. The first transistor (301) has a drain connection to the first node (N1) and a source connection to the intermediate node (N3). The second transistor (302) has a drain connection to the second node (N2) and a source connection to the intermediate node (N3). The third transistor (303) has a source connection to the defined voltage (VS) and a drain connection to the intermediate node (N3) and regulates the voltage at the intermediate node when the switch arrangement is in an off state.
-
公开(公告)号：US20170251294A1
公开(公告)日：2017-08-31
申请号：US15439323
申请日：2017-02-22
发明人： Rupesh KHARE
CPC分类号： H04R1/1041 , H03F3/00 , H03F3/187 , H03F2200/03 , H03F2200/441 , H03G3/341 , H03G3/348 , H03K19/018507 , H04R3/00 , H04R2420/01
摘要： This application describes methods and apparatus for selectively clamping a signal path (106) for an analogue audio signal to a clamp voltage, e.g. ground. Voltage clamping circuitry (200) is disclosed having a first switching device (201) in series with a second switching device (202) between a node of the signal path and the clamp voltage. The clamping circuitry is configured to be operable in: a first state where the first and second switching devices are both on to electrically connect the signal path to the clamp voltage; and also a second state to electrically disconnect the signal path from the clamp voltage. In the second state one of the first and second switching devices is configured to block conduction when the voltage at said node of the signal path is positive and the other switching device is configured to block conduction when the voltage at said node of the signal path is negative.
-
-
-
-
搜索结果
5 条记录 (耗时 0.016 秒)
