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    Transmission-line resistance compression networks and related techniques
    3.
    发明授权
    Transmission-line resistance compression networks and related techniques 有权
    传输线电阻压缩网络及相关技术

    公开(公告)号：US09531291B2

    公开(公告)日：2016-12-27

    申请号：US14255427

    申请日：2014-04-17

    Applicant: Eta Devices, Inc.

    Inventor： David J. Perreault

    IPC: H03H7/38 ,  H02M7/217 ,  H03F3/00 ,  H02M7/06 ,  H03F3/195 ,  H03F3/21 ,  H03F3/24 ,  H03F3/60

    CPC classification number: H02M7/217 ,  H02M7/06 ,  H03F1/02 ,  H03F3/00 ,  H03F3/195 ,  H03F3/211 ,  H03F3/24 ,  H03F3/245 ,  H03F3/602 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/192 ,  H03F2200/204 ,  H03F2200/462 ,  H03H7/38 ,  Y10T307/25

    Abstract: Described embodiments provide a transmission-line resistance compression network that includes an input port, a first output port coupled to a first load and a second output port coupled to a second load. The first and second loads may have substantially similar input impedances under substantially similar operating conditions. The transmission-line resistance compression network includes a transmission-line network coupled to the input port, the first output port and the second output port, and includes at least two transmission lines of different lengths. For a first operating range, the resistances at input ports of the first and second loads vary over first and second ratios, respectively. The resistance of the input impedance at the input port of the transmission-line resistance compression network varies over a third ratio that is smaller than at least one of the first and second ratios.

    Abstract translation: 描述的实施例提供一种传输线路电阻压缩网络，其包括输入端口，耦合到第一负载的第一输出端口和耦合到第二负载的第二输出端口。 在基本相似的操作条件下，第一和第二负载可具有基本类似的输入阻抗。 传输线电阻压缩网络包括耦合到输入端口，第一输出端口和第二输出端口的传输线网络，并且包括至少两根不同长度的传输线。 对于第一操作范围，第一和第二负载的输入端口处的电阻分别在第一和第二比率上变化。 在传输线路电阻压缩网络的输入端口处的输入阻抗的电阻变化小于第一和第二比率中的至少一个比率的第三比率。

    ELECTRONIC CIRCUIT
    4.
    发明申请
    ELECTRONIC CIRCUIT 有权
    电子电路

    公开(公告)号：US20150029049A1

    公开(公告)日：2015-01-29

    申请号：US14321644

    申请日：2014-07-01

    Applicant: FUJITSU LIMITED

    Inventor： Takumi DANJO

    IPC: H03M1/12

    CPC classification number: H03K5/2481 ,  H03F3/00 ,  H03K5/249

    Abstract: An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned ON in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal.

    Abstract translation: 电子电路包括：一对第一晶体管，其中第一控制信号被输入到第一控制端中的至少一个; 比较器电路，其基于流过所述一对第一晶体管的电流来设定一对差分输出端子的电位; 第二晶体管，其串联地耦合在来自所述一对差分输出端子中的至少一个的电源和节点之间的路径中，并且在相应的一对第一晶体管之间并且具有第二控制端子，第二控制信号 被输入 第一开关分别串联耦合到路径中的第二晶体管并且与时钟信号同步地导通; 以及基于时钟信号产生第二控制信号的发生电路。

    Switched mode assisted linear regulator with decoupled output impedance and signal path bandwidth
    7.
    发明授权
    Switched mode assisted linear regulator with decoupled output impedance and signal path bandwidth 有权
    开关模式辅助线性稳压器，具有去耦输出阻抗和信号路径带宽

    公开(公告)号：US09276475B2

    公开(公告)日：2016-03-01

    申请号：US13963407

    申请日：2013-08-09

    Applicant: Texas Instruments Incorporated

    Inventor： Carsten Barth ,  John Hoversten ,  Steven Berg ,  Vahid Yousefzadeh ,  Arie Van Staveren ,  Bert Helleman

    IPC: H02M3/158 ,  H02M1/00 ,  H02M3/156

    CPC classification number: H02M3/1584 ,  G01F1/00 ,  H02M3/1588 ,  H02M5/293 ,  H02M2001/0045 ,  H02M2003/1566 ,  H03F1/0227 ,  H03F3/00 ,  H03F3/2173 ,  H03F2200/432 ,  Y02B70/1466

    Abstract: A switched mode assisted linear (SMAL) amplifier/regulator architecture can be configured to supply regulated power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator can include a linear amplifier and a switched mode converter parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched converter are cooperatively controlled to supply load current. The amplifier can include separate feedback loops: an external relatively lower speed feedback loop for controlling signal path bandwidth, and an internal relatively higher speed feedback loop for controlling output impedance bandwidth of the linear amplifier. The linear amplifier can be AC coupled to the supply node, and the switched converter can be configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control.

    Abstract translation: 开关模式辅助线性（SMAL）放大器/调节器架构可以配置为向动态负载（例如RF功率放大器）提供稳压电源。 SMAL调节器的实施例可以包括在供电节点处并联耦合的线性放大器和开关模式转换器，并且被配置为使得放大器设置负载电压，同时协调地控制放大器和开关转换器以提供负载电流。 放大器可以包括单独的反馈回路：用于控制信号路径带宽的外部相对较低速度的反馈回路，以及用于控制线性放大器的输出阻抗带宽的内部相对较高速度的反馈回路。 线性放大器可以交流耦合到电源节点，并且开关转换器可以配置有电容性电荷控制环路，其控制开关转换器以有效地控制放大器以提供电容充电控制。

    Electronic circuit
    8.
    发明授权
    Electronic circuit 有权
    电子电路

    公开(公告)号：US09154120B2

    公开(公告)日：2015-10-06

    申请号：US14321644

    申请日：2014-07-01

    Applicant: FUJITSU LIMITED

    Inventor： Takumi Danjo

    IPC: H03K19/0175 ,  H03K5/24 ,  H03F3/00

    CPC classification number: H03K5/2481 ,  H03F3/00 ,  H03K5/249

    Abstract: An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned ON in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal.

    Abstract translation: 电子电路包括：一对第一晶体管，其中第一控制信号被输入到第一控制端中的至少一个; 比较器电路，其基于流过所述一对第一晶体管的电流来设定一对差分输出端子的电位; 第二晶体管，其串联地耦合在来自所述一对差分输出端子中的至少一个的电源和节点之间的路径中，并且在相应的一对第一晶体管之间并且具有第二控制端子，第二控制信号 被输入 第一开关分别串联耦合到路径中的第二晶体管并且与时钟信号同步地导通; 以及基于时钟信号产生第二控制信号的发生电路。

    LOW NOISE AMPLIFIER AND RECEIVER
    9.
    发明申请
    LOW NOISE AMPLIFIER AND RECEIVER 有权
    低噪声放大器和接收器

    公开(公告)号：US20150280672A1

    公开(公告)日：2015-10-01

    申请号：US14228661

    申请日：2014-03-28

    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.

    Inventor： JAW-MING DING ,  JIA-HONG MOU

    IPC: H03G3/30 ,  H03F1/02 ,  H03F3/19

    CPC classification number: H03G3/3036 ,  H03F1/0205 ,  H03F1/223 ,  H03F3/00 ,  H03F3/19 ,  H03F3/193 ,  H03F2200/294 ,  H03F2200/451

    Abstract: A low noise amplifier is disclosed. The low noise amplifier comprises a current mirror circuit, a bias circuit, a cascode amplifying circuit and a power gain compensating circuit. The current mirror circuit is used for providing a first current and third current. The bias circuit is used for receiving a first current and third current and outputting a first bias voltage and a second bias voltage according to the first current and third current. The cascode amplifying circuit respectively receives the first bias voltage and the second bias voltage, and accordingly to work at an operation bias point. The power gain compensating circuit is used for receiving a RF output signal and accordingly outputs a gain compensating signal to the current mirror circuit so as to dynamically adjust current value of the first current and third current and further to compensates power gain of the low noise amplifier in order to increase 1 dB gain compression point (P1dB).

    Abstract translation: 公开了一种低噪声放大器。 低噪声放大器包括电流镜电路，偏置电路，共源共栅放大电路和功率增益补偿电路。 电流镜电路用于提供第一电流和第三电流。 偏置电路用于接收第一电流和第三电流，并且根据第一电流和第三电流输出第一偏置电压和第二偏置电压。 共源共栅放大电路分别接收第一偏置电压和第二偏置电压，并因此在工作偏压点工作。 功率增益补偿电路用于接收RF输出信号，并且相应地向电流镜电路输出增益补偿信号，以便动态地调节第一电流和第三电流的电流值，并进一步补偿低噪声放大器的功率增益 以增加1 dB增益压缩点（P1dB）。

    SWITCHABLE CURRENT SOURCE CIRCUIT AND METHOD
    10.
    发明申请
    SWITCHABLE CURRENT SOURCE CIRCUIT AND METHOD 有权
    可切换电流源电路和方法

    公开(公告)号：US20140312963A1

    公开(公告)日：2014-10-23

    申请号：US14201581

    申请日：2014-03-07

    Applicant: NXP B.V.

    Inventor： Marco Berkhout

    IPC: G05F3/02

    CPC classification number: G05F3/02 ,  G05F3/262 ,  H03F3/00 ,  H03K17/04206

    Abstract: a switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.

    Abstract translation: 其中采样并存储用于驱动输出晶体管的栅极的参考电压值的可切换电流源。 使用馈送电流感测晶体管的参考电流源导出参考电压。 当输出晶体管截止时，电流检测晶体管截止，使得参考电流源不消耗功率。 然后可以在短时间内使用大的参考电流Iref。

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