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    Dual storage cell memory
    1.
    发明授权
    Dual storage cell memory 失效
    双存储单元存储器

    公开(公告)号：US6118690A

    公开(公告)日：2000-09-12

    申请号：US563152

    申请日：1995-11-27

    Applicant: Ching-Lin Jiang ,  Clark R. Williams

    Inventor： Ching-Lin Jiang ,  Clark R. Williams

    IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/419

    CPC classification number: G06F5/065 ,  G11C11/41 ,  G11C11/412 ,  G11C19/287 ,  G11C8/16

    Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

    Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。

    Dual storage cell memory including data transfer circuits
    3.
    发明授权
    Dual storage cell memory including data transfer circuits 失效
    双存储单元存储器，包括数据传输电路

    公开(公告)号：US4873665A

    公开(公告)日：1989-10-10

    申请号：US203424

    申请日：1988-06-07

    Applicant: Ching-Lin Jiang ,  Clark R. Williams

    Inventor： Ching-Lin Jiang ,  Clark R. Williams

    IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28

    CPC classification number: G11C11/412 ,  G06F5/065 ,  G11C11/41 ,  G11C19/287 ,  G11C8/16

    Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

    Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。

    Dual port static RAM with bidirectional shift capability
    6.
    发明授权
    Dual port static RAM with bidirectional shift capability 失效
    具有双向移位功能的双端口静态RAM

    公开(公告)号：US5299156A

    公开(公告)日：1994-03-29

    申请号：US542689

    申请日：1990-06-25

    Applicant: Ching-Lin Jiang ,  Clark R. Williams

    Inventor： Ching-Lin Jiang ,  Clark R. Williams

    IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G06F5/065 ,  G11C11/41 ,  G11C19/287 ,  G11C8/16

    Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

    Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。

    Two-mode oscillator
    7.
    发明授权
    Two-mode oscillator 失效
    双模式振荡器

    公开(公告)号：US5150079A

    公开(公告)日：1992-09-22

    申请号：US717238

    申请日：1991-06-18

    Applicant: Clark R. Williams ,  Ching-Lin Jiang

    Inventor： Clark R. Williams ,  Ching-Lin Jiang

    IPC: H03B5/36

    CPC classification number: H03B5/364 ,  H03B2200/0012

    Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

    Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

    Low-power clock/calendar architecture
    9.
    发明授权
    Low-power clock/calendar architecture 失效
    低功耗时钟/日历架构

    公开(公告)号：US5175699A

    公开(公告)日：1992-12-29

    申请号：US264233

    申请日：1988-10-28

    Applicant: William J. Podkowa ,  Clark R. Williams

    Inventor： William J. Podkowa ,  Clark R. Williams

    IPC: G04G3/00 ,  G04G99/00

    CPC classification number: G04G99/006 ,  G04G3/00

    Abstract: An integrated circuit timekeeper, which uses a hybrid hardware/software architecture, wherein the least significant bits are updated in hardware and the more significant bits are updated in software. This hybrid architecture provides improved power efficiency, layout efficiency, and flexibility in reconfiguration.

    Abstract translation: 一种集成电路计时器，其使用混合硬件/软件架构，其中最低有效位在硬件中更新，并且更高有效位在软件中更新。 该混合架构提供了改进的功率效率，布局效率和重新配置的灵活性。

    Low power timekeeping system
    10.
    发明授权
    Low power timekeeping system 失效
    低功率计时系统

    公开(公告)号：US5050113A

    公开(公告)日：1991-09-17

    申请号：US208889

    申请日：1988-06-17

    Applicant: William J. Podkowa ,  Clark R. Williams

    Inventor： William J. Podkowa ,  Clark R. Williams

    IPC: G04G3/00 ,  G04G99/00

    CPC classification number: G04G99/006 ,  G04G3/00

    Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

    Abstract translation: 低功率计时系统利用状态机首先读取存储在RAM中的秒数，并更新秒数，然后确定分钟是否需要更新。 如果分钟不需要更新，则定序器将停止运行，直到下一个更新周期。 类似地，分钟，小时，星期几，月份，月份和年份的日期仅在每个更新周期中根据需要进行更新，从而降低计时系统所需的功率需求。

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