公开(公告)号：US5339076A

公开(公告)日：1994-08-16

申请号：US876771

申请日：1992-04-27

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G06F5/00 ,  G06F17/21 ,  G06T9/00 ,  H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3086 ,  G06T9/005

Abstract: A data compression/decompression processor implements a modified Ziv-Lempel ("LZ") coding technique. The processor includes three modules, an interface, a coder-decoder ("CODEC"), and a MODEL. The CODEC and the MODEL modules together form compression engine, in which the CODEC provides variable length coding and data packing, and the MODEL implements the LZ processing. The MODEL uses content addressable memory ("CAM") in encoding mode for text storage and character matching, and uses CAM in decoding mode as an on-chip RAM to obtain high speed access.

Abstract translation: 数据压缩/解压缩处理器实现修改的Ziv-Lempel（“LZ”）编码技术。 处理器包括三个模块，一个接口，一个编码器解码器（“CODEC”）和一个MODEL。 CODEC和MODEL模块一起形成压缩引擎，其中CODEC提供可变长度编码和数据打包，MODEL实现LZ处理。 MODEL在编码模式下使用内容可寻址存储器（“CAM”）进行文本存储和字符匹配，并将解码模式下的CAM用作片上RAM以获得高速访问。

公开(公告)号：US4894791A

公开(公告)日：1990-01-16

申请号：US828230

申请日：1986-02-10

Applicant: Ching-Lin Jiang ,  William J. Podkowa

Inventor： Ching-Lin Jiang ,  William J. Podkowa

IPC: H03K5/04 ,  H03K19/003

CPC classification number: H03K5/04 ,  H03K19/00323

Abstract: A delay circuit that can be implemented in a monolithic integrated circuit includes a plurality of capacitor/laser-fusible link series pairs. Delay of a binary output signal of the circuit with respect to an input transition is directly proportional to the amount of capacitance connected into the circuit. Because the laser-fusible links can selectively be opened with a laser, the amount of capacitance connected into the circuit can incrementally be reduced; thus, the delay of the circuit is reducibly adjustable to a desired value. By including a plurality of conductive element/laser-fusible link series pairs in the delay circuit, the delay of the circuit is also increasingly adjustable. A method for economically adjusting the delay of each of many like delay circuits embodied in a semiconductor wafer includes measuring a sample of the delays of the delay circuits, calculating an average delay, determining the difference between a desired delay and the average delay to determine an incremental amount of delay to eliminate or to add, determining from predetermined data which fusible links should be opened, and using a laser beam to open the appropriate links.

Abstract translation: 可以在单片集成电路中实现的延迟电路包括多个电容器/激光可熔链节串联对。 相对于输入跃迁的电路的二进制输出信号的延迟与连接到电路中的电容量成正比。 因为激光熔丝可以选择性地用激光打开，连接到电路中的电容量可以逐渐减小; 因此，电路的延迟可以可调节到期望的值。 通过在延迟电路中包括多个导电元件/激光可熔链节串联对，电路的延迟也越来越可调。 用于经济地调节在半导体晶片中实现的许多类似延迟电路中的每一个的延迟的方法包括测量延迟电路的延迟的样本，计算平均延迟，确定期望延迟和平均延迟之间的差以确定 消除或添加的增量的延迟量，从预定数据确定哪个可熔断链接应该被打开，以及使用激光束打开适当的链接。

公开(公告)号：US4545035A

公开(公告)日：1985-10-01

申请号：US400171

申请日：1982-07-20

Applicant: Daniel C. Guterman ,  Ching-Lin Jiang

Inventor： Daniel C. Guterman ,  Ching-Lin Jiang

IPC: G11C14/00 ,  H01L27/108 ,  G11C11/40

CPC classification number: H01L27/108 ,  G11C14/00

Abstract: A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.

Abstract translation: 紧凑型存储单元将易失性动态存储部分与两个垂直堆叠的元件阵列中的阴影非易失部分组合。

公开(公告)号：US4360903A

公开(公告)日：1982-11-23

申请号：US265994

申请日：1980-09-10

Applicant: Robert S. Plachno ,  Ching-Lin Jiang

Inventor： Robert S. Plachno ,  Ching-Lin Jiang

IPC: G11C11/406 ,  G11C11/4063 ,  G11C7/00

CPC classification number: G11C11/406 ,  G11C11/4063

Abstract: A clocking system for a self-refreshed dynamic memory (10) for reading data stored in a memory cell (30) and including clocking circuitry (68) includes detecting changes in an address signal (60). The method further includes generating a memory refresh signal (64, 66) in response to detecting changes in the address signal (60). The memory refresh signal (66) is applied to the semiconductor memory circuit (30) for refreshing data stored in the memory cells of the semiconductor memory circuit (30). After the application of the memory refresh signal (66) to the semiconductor memory circuit (30) the address signal (16) is applied to the semiconductor memory circuit (30) for accessing the addressed memory cell to thereby read the data stored therein. The clocking circuitry (68) is reset and precharged during the application of the refresh signal (66) to the semiconductor memory circuit (30).

Abstract translation: PCT No.PCT / US80 / 01162 Sec。 371日期1980年9月10日 102（e）1980年9月10日PCT PCT日期为1980年9月10日PCT公布。 第WO82 / 00915号公报 日期：1982年3月18日。一种用于读取存储在存储单元（30）中并包括时钟电路（68）的数据的自动刷新动态存储器（10）的计时系统，包括检测地址信号（60）中的变化。 该方法还包括响应于检测到地址信号（60）中的变化而产生存储器刷新信号（64,66）。 存储器刷新信号（66）被施加到半导体存储器电路（30），用于刷新存储在半导体存储器电路（30）的存储单元中的数据。 在向半导体存储器电路（30）施加存储器刷新信号（66）之后，将地址信号（16）施加到半导体存储器电路（30），以访问所寻址的存储器单元，从而读取存储在其中的数据。 在刷新信号（66）施加到半导体存储器电路（30）期间，时钟电路（68）被复位并被预充电。

公开(公告)号：US4306221A

公开(公告)日：1981-12-15

申请号：US25138

申请日：1979-03-29

Applicant: Ching-Lin Jiang ,  Chi-Shin Wang

Inventor： Ching-Lin Jiang ,  Chi-Shin Wang

IPC: H03M1/00 ,  H03K13/03

CPC classification number: H03M1/14

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract translation: 通过逐次逼近的模数转换通过电荷耦合器件实现。 在转换过程中，比较两个电荷，每个比较产生一个多位数的一位。 通过在每次比较之后增加较小的比较电荷，消除了作为逐次逼近处理的一部分的电荷减去的需要。

公开(公告)号：US4171521A

公开(公告)日：1979-10-16

申请号：US802835

申请日：1977-06-02

Applicant: Chi-Shin Wang ,  Ching-Lin Jiang

Inventor： Chi-Shin Wang ,  Ching-Lin Jiang

IPC: H03M1/00 ,  H03K13/03

CPC classification number: H03M1/442

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract translation: 通过逐次逼近的模数转换通过电荷耦合器件实现。 在转换过程中，比较两个电荷，每个比较产生一个多位数的一位。 通过在每次比较之后增加较小的比较电荷，消除了作为逐次逼近处理的一部分的电荷减去的需要。

公开(公告)号：US4645943A

公开(公告)日：1987-02-24

申请号：US660937

申请日：1984-10-15

Applicant: John W. Smith, Jr. ,  Francis A. Scherpenberg ,  Ching-Lin Jiang ,  Michael L. Bolan

Inventor： John W. Smith, Jr. ,  Francis A. Scherpenberg ,  Ching-Lin Jiang ,  Michael L. Bolan

IPC: G06F1/30 ,  H02J9/06 ,  H02J9/02

CPC classification number: G06F1/30 ,  H02J9/061 ,  Y10T307/615 ,  Y10T307/625

Abstract: A space-saving back-up power supply apparatus has length and width dimensions substantially the same as those of a conventional integrated circuit connector. The apparatus includes sockets arranged on its top for making connection to a socket-pluggable integrated circuit such as a standard CMOS RAM, and the apparatus has pins extending from its bottom for making connection to a printed circuit board or connector of a host electronic system. Control circuitry and one or more batteries are located within the apparatus. The back-up power supply is operative to provide power to the socket-pluggable integrated circuit even if the normal power supply of the host electronic system is short-circuited. The control circuitry of the back-up power supply controls the chip enable signal and performs a battery test upon power-up.

Abstract translation: 节省空间的备用电源设备的长度和宽度尺寸基本上与传统的集成电路连接器相同。 该设备包括设置在其顶部的插座，用于连接到诸如标准CMOS RAM的插座可插拔集成电路，并且该设备具有从其底部延伸的引脚，用于连接到主机电子系统的印刷电路板或连接器。 控制电路和一个或多个电池位于设备内。 即使主机电子系统的正常电源短路，备用电源也可以为插座可插拔集成电路供电。 备用电源的控制电路控制芯片使能信号，并在上电时执行电池测试。

公开(公告)号：US4613959A

公开(公告)日：1986-09-23

申请号：US568960

申请日：1984-01-06

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G06F11/16 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003 ,  H03K19/173 ,  G11C7/00 ,  G06F11/00 ,  H01J19/82 ,  H03K17/82

CPC classification number: G11C29/83 ,  G06F11/16 ,  G11C17/16 ,  H03K19/00392

Abstract: A redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by blowing a pair of fuses.

Abstract translation: 在激活之前或之后消耗功率的冗余电路在通过吹一对保险丝而被激活时将一对输出节点从第一组互补逻辑电平切换到反相集合。

公开(公告)号：US5351208A

公开(公告)日：1994-09-27

申请号：US874489

申请日：1992-04-27

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory is provided that includes a memory cell and a first plurality of lines connected directly to the gates of access transistors to this memory cell. These access transistors are further connected to a second plurality of lines. The first and second plurality of lines each perform different functions during read, write, and comparison modes. In another embodiment of the present invention, p-channel transistors are used for a match transistor and its associated pass transistors.

Abstract translation: 提供了一种内容可寻址存储器，其包括存储单元和直接连接到存储单元的存取晶体管的栅极的第一多条线。 这些存取晶体管进一步连接到第二组线。 第一和第二组线在读，写和比较模式下都执行不同的功能。 在本发明的另一个实施例中，p沟道晶体管用于匹配晶体管及其相关联的传输晶体管。

公开(公告)号：US5299156A

公开(公告)日：1994-03-29

申请号：US542689

申请日：1990-06-25

Applicant: Ching-Lin Jiang ,  Clark R. Williams

Inventor： Ching-Lin Jiang ,  Clark R. Williams

IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28 ,  G11C11/419

CPC classification number: G11C11/412 ,  G06F5/065 ,  G11C11/41 ,  G11C19/287 ,  G11C8/16

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。