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1.发明申请METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH 审中-公开使用选择性外延硅片后蚀刻形成具有低于50Nm STI结构的CMOS电路的方法公开(公告)号：US20090096055A1
公开(公告)日：2009-04-16
申请号：US12187958
申请日：2008-08-07
IPC分类号： H01L21/762 , H01L23/00
CPC分类号： H01L21/76232
摘要： An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width.
摘要翻译： 公开了一种IC中的STI场氧化物元件，其包括在STI沟槽的侧壁上的外延半导体层，以增加与STI沟槽相邻的有源区的宽度并减小STI沟槽中的介电材料的宽度。 在外延层生长之前，STI蚀刻残留物从STI沟槽表面去除。 外延半导体组合物与相邻有源区的组成相匹配。 外延半导体可以是未掺杂的或掺杂的以匹配有源区。 具有外延层的STI沟槽与常见的STI钝化和填充工艺兼容。 选择生长的外延半导体层的厚度以提供期望的有源面积宽度或期望的STI电介质宽度。
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公开(公告)号：US20090098702A1
公开(公告)日：2009-04-16
申请号：US12253095
申请日：2008-10-16
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L21/3086 , H01L21/76224
摘要： A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation sidewall spacers reduce the exposed substrate width during the subsequent STI trench etch process, leading to a reduced STI trench width. A method of forming the isolation sidewall spacers of a material that is easily removed from the isolation hardmask to provide an exposed shoulder width on the substrate defined by the sidewall thickness is also disclosed.
摘要翻译： 公开了一种使用隔离硬掩模上的侧壁间隔来形成减小宽度的STI场氧化物元件以减少STI沟槽宽度的方法。 通过在隔离硬掩模上沉积间隔物材料的共形层并执行各向异性蚀刻来形成隔离侧壁间隔物。 隔离侧壁间隔物在随后的STI沟槽蚀刻工艺期间减少暴露的衬底宽度，导致减小的STI沟槽宽度。 还公开了一种形成隔离侧壁间隔物的方法，该材料容易从隔离硬掩模中移除，以在由侧壁厚度限定的衬底上提供暴露的肩宽。
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公开(公告)号：US20100261298A1
公开(公告)日：2010-10-14
申请号：US12757704
申请日：2010-04-09
CPC分类号： H01L21/26506 , H01L21/02532 , H01L21/02658 , H01L21/02667 , H01L22/12 , H01L22/20
摘要： A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.
摘要翻译： 一种用于减小具有半导体表面的晶片的曲率的方法。 识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。 晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时具有晶体损伤的情况下，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间， 足以使非晶表面区域再结晶的温度。 由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。
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公开(公告)号：US08252609B2
公开(公告)日：2012-08-28
申请号：US12757704
申请日：2010-04-09
CPC分类号： H01L21/26506 , H01L21/02532 , H01L21/02658 , H01L21/02667 , H01L22/12 , H01L22/20
摘要： A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.
摘要翻译： 一种用于减小具有半导体表面的晶片的曲率的方法。 识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。 晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时与晶体有害的同时，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间， 足以使非晶表面区域再结晶的温度。 由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。
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公开(公告)号：US08216945B2
公开(公告)日：2012-07-10
申请号：US12757665
申请日：2010-04-09
IPC分类号： H01L21/311 , H01L21/469 , H01L21/31
CPC分类号： H01L22/20 , G03F7/70616 , G03F7/70783 , G03F7/70875 , H01L22/12
摘要： A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.
摘要翻译： 一种用于在光刻图案级别之间控制晶片的平坦度的方法。 在晶片的顶侧半导体表面上进行第一光刻步骤。 获得晶片的参考曲率信息。 参考曲率不是平面的。 执行至少一个处理步骤，其导致相对于参考曲率改变的曲率。 获得用于晶片的变化的曲率信息。 修改了晶片底部表面上的应力，减小了改变的曲率和参考曲率之间的差异。 在存在改性应力分布的同时，在顶侧半导体表面上进行第二光刻步骤。
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公开(公告)号：US20100261353A1
公开(公告)日：2010-10-14
申请号：US12757665
申请日：2010-04-09
IPC分类号： H01L21/465 , H01L21/46
CPC分类号： H01L22/20 , G03F7/70616 , G03F7/70783 , G03F7/70875 , H01L22/12
摘要： A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.
摘要翻译： 一种用于在光刻图案级别之间控制晶片的平坦度的方法。 在晶片的顶侧半导体表面上进行第一光刻步骤。 获得晶片的参考曲率信息。 参考曲率不是平面的。 执行至少一个处理步骤，其导致相对于参考曲率改变的曲率。 获得用于晶片的变化的曲率信息。 修改了晶片底部表面上的应力，减小了改变的曲率和参考曲率之间的差异。 在存在改性应力分布的同时，在顶侧半导体表面上进行第二光刻步骤。
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