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    METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH
    1.
    发明申请
    METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH 审中-公开
    使用选择性外延硅片后蚀刻形成具有低于50Nm STI结构的CMOS电路的方法

    公开(公告)号：US20090096055A1

    公开(公告)日：2009-04-16

    申请号：US12187958

    申请日：2008-08-07

    申请人： Clint L. Montgomery ,  Brian K. Kirkpatrick ,  Weize Xiong ,  Steven L. Prins

    发明人： Clint L. Montgomery ,  Brian K. Kirkpatrick ,  Weize Xiong ,  Steven L. Prins

    IPC分类号： H01L21/762 ,  H01L23/00

    CPC分类号： H01L21/76232

    摘要： An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width.

    摘要翻译： 公开了一种IC中的STI场氧化物元件，其包括在STI沟槽的侧壁上的外延半导体层，以增加与STI沟槽相邻的有源区的宽度并减小STI沟槽中的介电材料的宽度。 在外延层生长之前，STI蚀刻残留物从STI沟槽表面去除。 外延半导体组合物与相邻有源区的组成相匹配。 外延半导体可以是未掺杂的或掺杂的以匹配有源区。 具有外延层的STI沟槽与常见的STI钝化和填充工艺兼容。 选择生长的外延半导体层的厚度以提供期望的有源面积宽度或期望的STI电介质宽度。

    Method to Form CMOS Circuits Using Optimized Sidewalls
    2.
    发明申请
    Method to Form CMOS Circuits Using Optimized Sidewalls 审中-公开
    使用优化侧壁形成CMOS电路的方法

    公开(公告)号：US20090098702A1

    公开(公告)日：2009-04-16

    申请号：US12253095

    申请日：2008-10-16

    申请人： Brian K. Kirkpatrick ,  Weize Xiong ,  Steven L. Prins

    发明人： Brian K. Kirkpatrick ,  Weize Xiong ,  Steven L. Prins

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/3086 ,  H01L21/76224

    摘要： A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation sidewall spacers reduce the exposed substrate width during the subsequent STI trench etch process, leading to a reduced STI trench width. A method of forming the isolation sidewall spacers of a material that is easily removed from the isolation hardmask to provide an exposed shoulder width on the substrate defined by the sidewall thickness is also disclosed.

    摘要翻译： 公开了一种使用隔离硬掩模上的侧壁间隔来形成减小宽度的STI场氧化物元件以减少STI沟槽宽度的方法。 通过在隔离硬掩模上沉积间隔物材料的共形层并执行各向异性蚀刻来形成隔离侧壁间隔物。 隔离侧壁间隔物在随后的STI沟槽蚀刻工艺期间减少暴露的衬底宽度，导致减小的STI沟槽宽度。 还公开了一种形成隔离侧壁间隔物的方法，该材料容易从隔离硬掩模中移除，以在由侧壁厚度限定的衬底上提供暴露的肩宽。

    Disposable Spacer Integration with Stress Memorization Technique and Silicon-Germanium
    3.
    发明申请
    Disposable Spacer Integration with Stress Memorization Technique and Silicon-Germanium 有权
    一次性间隔与应力记忆技术和硅锗的整合

    公开(公告)号：US20110070703A1

    公开(公告)日：2011-03-24

    申请号：US12549862

    申请日：2009-08-28

    申请人： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

    发明人： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

    摘要翻译： 一种用于使用应力存储技术（SMT）层（126）形成NMOS晶体管（104）和嵌入式SiGe（eSiGe）PMOS晶体管（102）的集成工艺流程。 SMT层（126）沉积在NMOS晶体管（104）和PMOS晶体管（102）两者之上。 在PMOS晶体管（102）上方的SMT层（126）的部分被各向异性蚀刻以形成间隔物（128），而不通过NMOS晶体管（104）蚀刻SMT层（126）的部分。 间隔物（128）用于对准SiGe凹陷蚀刻和生长以形成SiGe源极/漏极区域（132）。 在蚀刻SMT层（126）之后执行源极/漏极退火，使得SMT层（126）在不降低PMOS晶体管（102）的情况下向NMOS晶体管（104）提供期望的应力。

    DUAL METAL GATES FOR MUGFET DEVICE
    6.
    发明申请
    DUAL METAL GATES FOR MUGFET DEVICE 有权
    双金属门为MUGFET设备

    公开(公告)号：US20080272433A1

    公开(公告)日：2008-11-06

    申请号：US11744322

    申请日：2007-05-04

    申请人： Husam Niman Alshareef ,  Weize Xiong

    发明人： Husam Niman Alshareef ,  Weize Xiong

    IPC分类号： H01L21/12 ,  H01L21/84

    CPC分类号： H01L27/1211 ,  H01L21/28088 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

    摘要： Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al2O3, and/or AlN overlaid by a second-metal-containing material such as TaN, TiN, WN, MoN or their respective metals. The reaction between the stacked layers can create a metal gate material with a desired work function value ranging from about 4.35 eV to about 5.0 eV. The disclosed methods and structures can be used for CMOS transistors including MOSFET devices formed on a bulk substrate, and planar FET devices or 3-D MuGFET devices (e.g., FinFET devices) formed upon the oxide insulator of a SOI.

    摘要翻译： 示例性实施例提供了用于控制用于晶体管器件的双金属栅电极的功函数值的方法和结构。 具体地，PMOS和NMOS金属栅电极之一的功函数值可以通过沉积在栅介电材料上的堆叠层之间的反应来控制。 堆叠层可以包括第一含金属的材料，例如Al 2 O 3 N，和/或由包含第二金属的材料如TaN覆盖的AlN， TiN，WN，MoN或它们各自的金属。 堆叠层之间的反应可产生具有约4.35eV至约5.0eV范围内的期望功函数值的金属栅极材料。 公开的方法和结构可以用于包括形成在体衬底上的MOSFET器件的CMOS晶体管，以及形成在SOI的氧化物绝缘体上的平面FET器件或3-D MuGFET器件（例如，FinFET器件）。

    Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate
    8.
    发明授权
    Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate 有权
    消除在DSB衬底的固相外延期间产生的再结晶边界缺陷的方法

    公开(公告)号：US08043947B2

    公开(公告)日：2011-10-25

    申请号：US11941187

    申请日：2007-11-16

    申请人： Angelo Pinto ,  Weize Xiong ,  Manfred Ramin

    发明人： Angelo Pinto ,  Weize Xiong ,  Manfred Ramin

    IPC分类号： H01L21/425

    CPC分类号： H01L21/187 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/76224

    摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.

    摘要翻译： 一种用于半导体处理的方法提供了具有第一晶体取向，第二晶体取向和设置在第一和第二晶体取向之间的边界区域的DSB半导体本体。 边界区域还具有与第一晶体取向和第二晶体取向的界面相关联的缺陷，其中缺陷通常从身体的表面延伸到半导体本体中的距离。 从其表面去除半导体本体的牺牲部分，其中去除牺牲部分至少部分地去除缺陷。 牺牲部分可以通过在低温下氧化表面来限定，其中氧化至少部分地消耗缺陷。 牺牲部分也可以通过CMP去除。 在去除牺牲部分之后，可以在缺陷上进一步形成STI特征，其中消耗任何剩余的缺陷。

    Multiple-gate MOSFET device and associated manufacturing methods
    9.
    发明授权
    Multiple-gate MOSFET device and associated manufacturing methods 有权
    多栅MOSFET器件及相关制造方法

    公开(公告)号：US07960234B2

    公开(公告)日：2011-06-14

    申请号：US11726516

    申请日：2007-03-22

    申请人： Craig Henry Huffman ,  Weize Xiong ,  Cloves Rinn Cleavelin

    发明人： Craig Henry Huffman ,  Weize Xiong ,  Cloves Rinn Cleavelin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7853

    摘要： One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.

    摘要翻译： 本发明的一个实施例涉及一种制造多栅极晶体管的方法。 在该方法期间，从形成多栅极晶体管的半导体结构中选择性地去除第二栅电极材料，从而暴露第一栅电极材料的至少一个表面。 第一栅电极材料的暴露表面被去角质化。 随后，去除第一栅电极材料。 还公开了其它方法和装置。