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1.发明申请System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry 有权增加内存自检内存和电路范围的系统和方法公开(公告)号：US20100229056A1
公开(公告)日：2010-09-09
申请号：US12784078
申请日：2010-05-20
CPC分类号： G11C29/76 , G11C29/44 , G11C2029/0401 , G11C2029/1208
摘要： An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.
摘要翻译： 集成电路（IC），IC的测试方法和从含有内置自检（BIST）电路的IC读取测试结果的方法。 在一个实施例中，IC包括：（1）外部测试总线接口，（2）耦合到外部测试总线接口的读写存储器，（3）耦合到外部测试总线的其他电路和（4）BIST电路 接口，读写存储器和其他电路，并且被配置为测试读写存储器以识别其中的良好数据块，将读写存储器中的预定数据块存储到指向良好数据块的多个实例中 ，至少对其他电路进行测试，并将至少一些测试结果存储在良好的数据块中。
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2.发明授权公开(公告)号：US07752518B2
公开(公告)日：2010-07-06
申请号：US12030365
申请日：2008-02-13
CPC分类号： G11C29/76 , G11C29/44 , G11C2029/0401 , G11C2029/1208
摘要： An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.
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3.发明申请System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry 有权增加内存自检内存和电路范围的系统和方法公开(公告)号：US20090204861A1
公开(公告)日：2009-08-13
申请号：US12030365
申请日：2008-02-13
IPC分类号： G01R31/28
CPC分类号： G11C29/76 , G11C29/44 , G11C2029/0401 , G11C2029/1208
摘要： An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.
摘要翻译： 集成电路（IC），IC的测试方法和从含有内置自检（BIST）电路的IC读取测试结果的方法。 在一个实施例中，IC包括：（1）外部测试总线接口，（2）耦合到外部测试总线接口的读写存储器，（3）耦合到外部测试总线的其他电路和（4）BIST电路 接口，读写存储器和其他电路，并且被配置为测试读写存储器以识别其中的良好数据块，将读写存储器中的预定数据块存储到指向良好数据块的多个实例中 ，至少对其他电路进行测试，并将至少一些测试结果存储在良好的数据块中。
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4.发明授权System and method for increasing the extent of built-in self-testing of memory and circuitry 有权用于增加内存和电路内置自检的程度的系统和方法公开(公告)号：US07793186B1
公开(公告)日：2010-09-07
申请号：US12784078
申请日：2010-05-20
CPC分类号： G11C29/76 , G11C29/44 , G11C2029/0401 , G11C2029/1208
摘要： An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.
摘要翻译： 集成电路（IC），IC的测试方法和从含有内置自检（BIST）电路的IC读取测试结果的方法。 在一个实施例中，IC包括：（1）外部测试总线接口，（2）耦合到外部测试总线接口的读写存储器，（3）耦合到外部测试总线的其他电路和（4）BIST电路 接口，读写存储器和其他电路，并且被配置为测试读写存储器以识别其中的良好数据块，将读写存储器中的预定数据块存储到指向良好数据块的多个实例中 ，至少对其他电路进行测试，并将至少一些测试结果存储在良好的数据块中。
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公开(公告)号：US07704883B2
公开(公告)日：2010-04-27
申请号：US11615456
申请日：2006-12-22
申请人： Stephanie W. Butler , Yuanning Chen
发明人： Stephanie W. Butler , Yuanning Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28247 , H01L21/268 , H01L21/28035 , H01L21/28123 , H01L29/665 , H01L29/6659
摘要： A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.
摘要翻译： 一种半导体器件的制造方法。 该方法包括在半导体衬底上沉积材料层并用图案材料图案化材料层。 图案化形成半导体器件的图案化结构，其中图案化结构具有与其相关联的粗糙度的侧壁。 该方法还包括从图案化结构中去除图形材料，并退火图案化结构的外表面，使得粗糙度减小。
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6.发明授权System and method for monitoring and evaluating semiconductor wafer fabrication 失效用于监控和评估半导体晶圆制造的系统和方法
公开(公告)号：US5399229A
公开(公告)日：1995-03-21
申请号：US61983
申请日：1993-05-13
IPC分类号： H01L21/02 , H01L21/302 , H01L21/3065 , H01L21/66 , H01L21/306 , B44C1/22
CPC分类号： H01L22/20 , B24B37/013 , H01L22/26 , H01L22/12 , H01L2924/0002
摘要： A system (60) and method for monitoring, evaluating and controlling the uniformity of a semiconductor wafer fabrication process is provided for use in manufacturing integrated circuits on semiconductor wafers (40). By using in situ ellipsometry (20) in conjunction with statistical modeling methods, the spatial etch rate pattern across a semiconductor wafer (40) may be inferred as a function of the process conditions. A predicted mean etch rate may be calculated for other locations (46 and 48) on the semiconductor wafer surface (42) by using the mean etch rate measured at the selected ellipsometer site (44) and individual spatial etch rate models developed for each site (44 and 48) based on statistically designed experiments. The predicted mean etch rate at the other sites (46 and 48) is also a function of the fabrication process conditions. The method for evaluating uniformity may be used with fabrication processes such as oxidation, doping, etching or any other process which may be measured in situ at a selected location (44) on a semiconductor wafer (40) during the fabrication process.
摘要翻译： 提供了用于监控，评估和控制半导体晶片制造工艺的均匀性的系统（60）和用于制造半导体晶片（40）上的集成电路的方法。 通过使用原位椭偏仪（20）结合统计建模方法，半导体晶片（40）之间的空间蚀刻速率图案可以作为工艺条件的函数推断。 可以通过使用在所选择的椭偏仪位置（44）处测量的平均蚀刻速率和为每个位置开发的各个空间蚀刻速率模型，来计算半导体晶片表面（42）上的其它位置（46和48）的预测平均蚀刻速率 44和48）基于统计学设计的实验。 在其他位置（46和48）处的预测平均蚀刻速率也是制造工艺条件的函数。 用于评估均匀性的方法可用于制造过程，例如氧化，掺杂，蚀刻或可在制造过程中在半导体晶片（40）上的选定位置（44）原位测量的任何其它工艺。
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7.发明授权Virtual sensor based monitoring and fault detection/classification system and method for semiconductor processing equipment 失效基于虚拟传感器的监控和故障检测/分类系统和半导体处理设备的方法
公开(公告)号：US5864773A
公开(公告)日：1999-01-26
申请号：US743113
申请日：1996-11-01
CPC分类号： H01L22/20
摘要： A virtual sensor based monitoring and fault detection/classification system (10) for semiconductor processing equipment (12) is provided. A plurality of equipment sensors (14) are each operable to measure a process condition and provide a signal representing the measured process condition. A plurality of filtering process units (16) are each operable to receive at least one signal from the plurality of equipment sensors (14) and to reduce data represented by the at least one signal and provide filtered data. A plurality of virtual sensors (24) are each operable to receive the filtered data. The plurality of virtual sensors (24) model states of the processing equipment (12) and a work piece in the processing equipment (12). Each virtual sensor is operable to provide an output signal representing an estimated value for the modeled state. A rule based logic system (26) is operable to receive and process the signals provided by the plurality of equipment sensors (14) and the output signals provided by the virtual sensors (24) to monitor processing equipment (12) or to detect and classify faults within the processing equipment (12).
摘要翻译： 提供了一种用于半导体处理设备（12）的基于虚拟传感器的监视和故障检测/分类系统（10）。 多个设备传感器（14）各自可操作以测量处理条件并提供表示所测量的处理条件的信号。 多个滤波处理单元（16）各自可操作以从多个设备传感器（14）接收至少一个信号，并且减少由至少一个信号表示的数据，并提供滤波数据。 多个虚拟传感器（24）各自可操作以接收经滤波的数据。 多个虚拟传感器（24）对处理设备（12）的状态和处理设备（12）中的工件进行建模。 每个虚拟传感器可操作以提供表示建模状态的估计值的输出信号。 基于规则的逻辑系统（26）可操作以接收和处理由多个设备传感器（14）提供的信号和由虚拟传感器（24）提供的输出信号以监视处理设备（12）或检测和分类 处理设备（12）内的故障。
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公开(公告)号：US5458732A
公开(公告)日：1995-10-17
申请号：US188653
申请日：1994-01-28
CPC分类号： B24B37/013 , H01J37/32174 , H01J37/32935 , H01L22/26
摘要： A plasma processing system 10 for fabricating a semiconductor wafer 24 is disclosed. The system includes a plasma processing tool 12 and an RF energy source 20 coupled to the plasma processing tool 12. An optional matching network 22 may be included between the RF energy source 20 and the plasma processing tool 12. Circuitry 18 for monitoring the RF energy to obtain a measurement characteristic is also provided. At least one transducer 14 or 16 is coupled between the plasma processing tool 12 and the circuitry 18 for monitoring the RF energy. The RF energy is typically applied at a fundamental frequency and the electrical characteristic is monitored at a second frequency different than the fundamental frequency. Also included is circuitry 19, such as a computer, for interpreting the measurement to determine a condition of the processing system 10. Other systems and methods are also disclosed.
摘要翻译： 公开了一种用于制造半导体晶片24的等离子体处理系统10。 该系统包括等离子体处理工具12和耦合到等离子体处理工具12的RF能量源20.可选的匹配网络22可以包括在RF能量源20和等离子体处理工具12之间。用于监测RF能量的电路18 也提供了测量特性。 至少一个换能器14或16耦合在等离子体处理工具12和电路18之间，用于监测RF能量。 RF能量通常以基本频率施加，并且以与基本频率不同的第二频率监测电特性。 还包括诸如计算机的电路19，用于解释测量以确定处理系统10的状况。还公开了其它系统和方法。
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公开(公告)号：US20080150045A1
公开(公告)日：2008-06-26
申请号：US11615456
申请日：2006-12-22
申请人： Stephanie W. Butler , Yuanning Chen
发明人： Stephanie W. Butler , Yuanning Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28247 , H01L21/268 , H01L21/28035 , H01L21/28123 , H01L29/665 , H01L29/6659
摘要： A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.
摘要翻译： 一种半导体器件的制造方法。 该方法包括在半导体衬底上沉积材料层并用图案材料图案化材料层。 图案化形成半导体器件的图案化结构，其中图案化结构具有与其相关联的粗糙度的侧壁。 该方法还包括从图案化结构中去除图形材料，并退火图案化结构的外表面，使得粗糙度减小。
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公开(公告)号：US06808997B2
公开(公告)日：2004-10-26
申请号：US10393749
申请日：2003-03-21
申请人： Amitabh Jain , Stephanie W. Butler
发明人： Amitabh Jain , Stephanie W. Butler
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/1083 , H01L29/7833
摘要： Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.
摘要翻译： 公开了使用多个离子注入步骤在半导体衬底中形成超浅结的方法。 离子注入步骤包括植入至少一种电子活性掺杂剂以及通过在掺杂剂注入期间通过沟槽化和/或通过热扩散来有效地限制结扩展的至少两种物质的注入。 在掺杂剂注入之后，电子活性掺杂剂通过热处理而被激活。
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