公开(公告)号：US20200266818A1

公开(公告)日：2020-08-20

申请号：US16795786

申请日：2020-02-20

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Bruce MILLAR

IPC: H03K19/00

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

公开(公告)号：US20150008956A1

公开(公告)日：2015-01-08

申请号：US14499275

申请日：2014-09-29

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Bruce MILLAR

IPC: H03K19/00 ,  H03H17/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/2254 ,  H03H7/38 ,  H03H17/0045 ,  H04L25/0278 ,  H04L25/028

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Abstract translation: 提供了执行片外驱动（OCD）和片上终端（ODT）的系统和方法。 由晶体管组成的公共上拉网络和由晶体管组成的公共下拉网络被采用来实现这两个功能。 在驱动模式下，上拉网络被配置为当要产生“开”输出时产生校准的驱动阻抗，并且当“关”输出为“关”时，上拉网络被配置为产生校准的驱动阻抗 生成。 在终端模式中，上拉网络和下拉网络被配置为分别产生校准的上拉电阻和下拉电阻，使得它们一起形成分离终端。

公开(公告)号：US20160277027A1

公开(公告)日：2016-09-22

申请号：US15079085

申请日：2016-03-24

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Bruce MILLAR

IPC: H03K19/00 ,  G11C11/4093 ,  H03H17/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/2254 ,  H03H7/38 ,  H03H17/0045 ,  H04L25/0278 ,  H04L25/028

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

公开(公告)号：US20180367140A9

公开(公告)日：2018-12-20

申请号：US15457680

申请日：2017-03-13

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Bruce MILLAR

IPC: H03K19/00

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

公开(公告)号：US20180262195A1

公开(公告)日：2018-09-13

申请号：US15457680

申请日：2017-03-13

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Bruce MILLAR

IPC: H03K19/00

CPC classification number: H03K19/0005

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

公开(公告)号：US20150078057A1

公开(公告)日：2015-03-19

申请号：US14546465

申请日：2014-11-18

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Peter B. GILLINGHAM ,  Bruce MILLAR

IPC: G11C5/06 ,  G11C8/18

CPC classification number: G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

Abstract translation: 一种包括缓冲器和多个同步存储器件的存储器模块。 存储器模块还包括双向总线，并且每个同步存储器件具有双向数据终端。 缓冲器被配置为重新生成在总线上接收的信号以供同步存储器件接收，并且重新产生从任何一个同步存储器装置接收的信号，以便由总线接收。 存储器模块还可以包括命令行和用于经由命令缓冲器向同步存储器件提供命令和时钟信号的时钟线。 存储器模块的组合数据总线宽度可以大于同步存储器件中任何一个的数据总线宽度，并且由存储器模块提供的总地址空间可能大于任何单个同步存储器件的数据空间。