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1.发明授权公开(公告)号：US07165132B1
公开(公告)日：2007-01-16
申请号：US10956650
申请日：2004-10-01
CPC分类号： G06F15/16
摘要： In one embodiment, a processing node includes a plurality of processor cores and a reconfigurable interconnect. The processing node also includes a controller configured to schedule transactions received from each processor core. The interconnect may be coupled to convey between a first processor core and the controller, transactions that each include a first corresponding indicator that indicates the source of the transaction. The interconnect may also be coupled to convey transactions between a second processor core and the controller, transactions that each include a second corresponding indicator that indicates the source of the transaction. When operating in a first mode, the interconnect is configurable to cause the first indicator to indicate that the corresponding transactions were conveyed from the second processor core and to cause the second indicator to indicate that the corresponding transactions were conveyed from the first processor core.
摘要翻译： 在一个实施例中，处理节点包括多个处理器核和可重配置互连。 处理节点还包括被配置为调度从每个处理器核心接收的事务的控制器。 互连可以被耦合以在第一处理器核心和控制器之间传送，每个事务包括指示事务源的第一对应指示符。 互连还可以被耦合以在第二处理器核心和控制器之间传送事务，每个事务包括指示事务源的第二对应指示符。 当以第一模式操作时，互连可配置为使得第一指示符指示相应的事务从第二处理器核心传送并使第二指示符指示对应的事务从第一处理器核心传送。
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公开(公告)号：US5541528A
公开(公告)日：1996-07-30
申请号：US519443
申请日：1995-08-25
IPC分类号： H03K19/20 , H03K19/017 , H03K19/0948
CPC分类号： H03K19/01721
摘要： A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal. When an appropriate voltage is applied to the power-down terminal, the pull-up transistor is turned off and the pull-down transistor is turned on such that no DC current flows in the circuit.
摘要翻译： 缓冲电路，其在二进制状态之间的转换中表现出增加的速度。 控制晶体管耦合在上拉晶体管和输入端之间。 在低至高输入信号转换期间，控制晶体管限制输入端子处的信号摆幅，使得输入端子电压的小变化导致输出端子处的较大的电压变化。 在这种转换期间，控制晶体管同时使输入端与上拉晶体管分离，从而使输入电容与上拉晶体管分离。 因此，上拉晶体管可以提高输出的速度增加。 随着希望处理的输入信号的数量增加，逻辑转换时间的减少变得更加显着。 一些版本还包括具有耦合到上拉晶体管的栅极的控制端子和掉电端子的下拉晶体管。 当向掉电端子施加适当的电压时，上拉晶体管截止，并且下拉晶体管导通，使得在该电路中不流过直流电流。
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公开(公告)号：US5297069A
公开(公告)日：1994-03-22
申请号：US929867
申请日：1992-08-13
CPC分类号： H03H17/06
摘要： Output data points of a digital FIR filter are calculated by storing input data points in an addressable memory and accessing the addressable memory to supply a new input data point exactly once for each output data point after a first output data point and storing each input data point in a first recirculating memory for so long as that input data point is needed to calculate a next output data point. The input data points stored in the first recirculating memory are used to calculate output data points. Furthermore, coefficients are stored in a second recirculating memory and are used to calculate the output data points. As a result, only one memory access is required per output data point.
摘要翻译： 通过将输入数据点存储在可寻址存储器中并访问可寻址存储器以在第一输出数据点之后为每个输出数据点提供一次新的输入数据点并存储每个输入数据点来计算数字FIR滤波器的输出数据点 在第一再循环存储器中，只要需要输入数据点来计算下一个输出数据点。 存储在第一再循环存储器中的输入数据点用于计算输出数据点。 此外，系数存储在第二再循环存储器中，并用于计算输出数据点。 因此，每个输出数据点只需要一个存储器访问。
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公开(公告)号：US5291457A
公开(公告)日：1994-03-01
申请号：US839192
申请日：1992-02-20
CPC分类号： H03K3/78
摘要： A sequentially accessible, non-volatile data storage circuit for generating constants includes a logic array for non-volatile storage of programmed data words and a recirculating shift register for causing the first one of the data words to appear at a data output of the data storage circuit in response to a reset signal and to cause the next data word to appear at the data output in response to a clock signal.
摘要翻译： 用于产生常数的可顺序访问的非易失性数据存储电路包括用于非易失性存储编程数据字的逻辑阵列和用于使第一数据字出现在数据存储器的数据输出端的再循环移位寄存器 响应于复位信号，并且响应于时钟信号使下一个数据字出现在数据输出端。
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5.发明授权Automated method of inserting pipeline stages in a data path element to achieve a specified operating frequency 失效在数据路径元素中插入流水线级以实现指定的工作频率的自动化方法
公开(公告)号：US5212782A
公开(公告)日：1993-05-18
申请号：US680004
申请日：1991-04-01
CPC分类号： G06F9/3869 , G06F17/5045 , G06F7/00
摘要： According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an the equation such as:D.sub.s =D.sub.b N.sub.b +Cwhere D.sub.s is the estimated stage delay, D.sub.b is a delay associated with communication between bits in the stage, N.sub.b is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.
摘要翻译： 根据用于通过多级数据通路元件确定延迟的技术，根据以下等式计算对数据通路元件的每个级的延迟的估计：Ds = DbNb + C其中Ds是估计级延迟，Db 是与阶段中的位之间的通信相关联的延迟，Nb是数据路径元素中的位数，C是常数。 估计的阶段延迟用于确定数据路径元素中流水线阶段的位置。
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