公开(公告)号：US5673221A

公开(公告)日：1997-09-30

申请号：US592939

申请日：1996-01-29

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：USRE38166E1

公开(公告)日：2003-07-01

申请号：US09410164

申请日：1999-09-30

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C1156

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m−2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：US5838612A

公开(公告)日：1998-11-17

申请号：US869072

申请日：1997-06-04

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

摘要： Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

摘要翻译： 用于多电平非易失性存储单元器件的读取电路，对于要读取的每个单元，具有与负载和去耦合和控制级相关联的选择线，其具有稳定选择线的电路节点上的电压的反馈环路 。 对该节点连接由反馈回路控制的当前复制电路。 这些包括与与存储器单元的选择线相关的负载和电路元件同源的负载和电路元件，并且具有用于连接到电流比较器电路的输出接口电路。

公开(公告)号：US5729490A

公开(公告)日：1998-03-17

申请号：US690059

申请日：1996-07-31

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C11/56 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632 ,  G11C2211/5633

摘要： A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current with a prescribed number of reference currents having values comprised between a minimum value and a maximum value of said discrete set of m cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current belongs; repeating step (a) for the sub-set of cell current values to which the cell current belongs, until the sub-set of cell current values to which the cell current belongs comprises only one cell current value, which is the value of the current of the memory cell to be sensed.

摘要翻译： 用于感测可以在多个m = 2n（n> = Z）个不同编程级别中采取一个编程电平的多级非易失性存储器单元的方法提供了在预定条件下偏置要感测的存储器单元，因此 存储器单元以具有m个不同单元电流值的离散集合的值吸收单元电流，每个单元电流值对应于所述编程电平之一。 感测方法还提供：同时将电池电流与规定数量的参考电流进行比较，所述规定数量的参考电流具有包括在所述离散的一组m个电池电流值的最小值和最大值之间的值，并且将所述离散的一组m个电池电流值 多个子单元电流子集，用于确定单元电流所属的单元电流值的子集; 对于单元电流所属的单元电流值的子集重复步骤（a），直到单元电流所属的单元电流值的子集仅包括一个单元电流值，该单元电流值是电流值 的待读取的存储单元。

公开(公告)号：US5701265A

公开(公告)日：1997-12-23

申请号：US593650

申请日：1996-01-29

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632

摘要： A serial dichotomic method for sensing multiple-level non-volatile memory cells which can take one of m=2.sup.n (n>=2) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, and for: a) comparing the cell current with a reference current which has a value comprised between a minimum value and a maximum value of said plurality of m cell current values, thus dividing said plurality of cell current values into two sub-pluralities of cell current values, and determining the sub-plurality of cell current values to which the cell current belongs; b) repeating the step a) until the sub-plurality of cell current values to which the cell current belongs comprises only one cell current value, which is the value for the current of the memory cell to be sensed.

摘要翻译： 用于感测可以采用m = 2n（n> = 2）个不同编程级中的一个的多级非易失性存储器单元的串行二分法方法提供在预定条件下偏置待感测的存储器单元，使得存储器 电池以具有多个m个不同电池电流值的值吸收电池电流，并且用于：a）将电池电流与参考电流进行比较，所述参考电流具有包含在所述多个m的最小值和最大值之间的值 电池电流值，从而将所述多个电池电流值分成两个多个电池电流值，并确定电池电流所属的电池电流值的子数量; b）重复步骤a），直到单元电流所属的单元电流值的子多个仅包含一个单元电流值，该单元电流值是要感测的存储单元的电流的值。

公开(公告)号：US5694363A

公开(公告)日：1997-12-02

申请号：US638976

申请日：1996-04-25

申请人： Cristiano Calligaro ,  Roberto Gastaldi ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Roberto Gastaldi ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C7/065

摘要： A device for reading memory cells, wherein the device contains two branches, wherein each branch comprises, connected in cascade, an electronic switch, an active element reactively connected to the active element of the other branch, so as to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element. A microswitch connects the two branches together is inserted between the two active elements.

摘要翻译： 一种用于读取存储器单元的装置，其中该装置包含两个分支，其中每个分支包括级联连接的电子开关，与另一分支的有源元件反应地连接的有源元件，以形成电压放大器。 每个有源元件通过高阻抗电路元件来控制。 将两个分支连接在一起的微动开关插入两个活动元件之间。

公开(公告)号：US5757719A

公开(公告)日：1998-05-26

申请号：US869208

申请日：1997-06-05

申请人： Cristiano Calligaro ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Paolo Cappelletti ,  Guido Torelli

发明人： Cristiano Calligaro ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Paolo Cappelletti ,  Guido Torelli

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C13/00

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632 ,  G11C2211/5634

摘要： A page-mode semiconductor memory device comprises a matrix of memory cells arranged in rows and columns, each row forming a memory page of the memory device and comprising at least one group of memory cells, memory page selection means for selecting a row of the matrix, and a plurality of sensing circuits each one associated with a respective column of the matrix. The memory cells are multiple-level memory cells which can be programmed in a plurality of c=2b(b>1) programming states to store b information bits, and the sensing circuits are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells, at each step one of said b information bits being determined, said at least one group of memory cells of a row forming a number b of memory words of a memory page.

摘要翻译： 页模式半导体存储器件包括以行和列排列的存储器单元矩阵，每行形成存储器件的存储器页，并且包括至少一组存储器单元，存储器页选择装置，用于选择矩阵的一行 ，以及多个感测电路，每个感测电路与矩阵的相应列相关联。 存储器单元是可以以多个c = 2b（b> 1）编程状态编程以存储b个信息位的多级存储器单元，并且感测电路是能够以数字确定的串行二分感测电路 b个连续近似步骤，存储在存储器单元中的b个信息位，在所确定的所述b个信息位的每个步骤中，所述至少一组形成存储器页的存储器字数b的存储单元组 。

公开(公告)号：US5986921A

公开(公告)日：1999-11-16

申请号：US883822

申请日：1997-06-27

申请人： Cristiano Calligaro ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  H03K5/13 ,  G11C13/00

CPC分类号： H03K5/13 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/32 ,  G11C2211/5644

摘要： A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block connected to an input terminal for memory address line transition signals. The delay block drives a counter which feedback controls the discharge through a combinational logic circuit connected to the output terminal of the programmable delay block. A logic output circuit, connected to the output terminal of the delay block and to the counter, generates the timing signals.

摘要翻译： 一种用于从包括多级非易失性存储器单元的器件读取的定时电路，该电路包括连接到用于存储器地址线转换信号的输入端的单个可编程延迟块。 延迟块驱动计数器，其反馈通过连接到可编程延迟块的输出端的组合逻辑电路来控制放电。 连接到延迟块的输出端和计数器的逻辑输出电路产生定时信号。

公开(公告)号：US5999445A

公开(公告)日：1999-12-07

申请号：US916874

申请日：1997-08-22

申请人： Paolo Rolandi ,  Cristiano Calligaro ,  Alessandro Manstretta ,  Guido Torelli

发明人： Paolo Rolandi ,  Cristiano Calligaro ,  Alessandro Manstretta ,  Guido Torelli

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/102 ,  G11C2211/5621

摘要： In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.

摘要翻译： 在多级类型的存储装置中，包括可通过地址输入寻址的多个存储器单元，每个单元适于在具有控制栅极的MOS晶体管中存储多于一个二进制信息元素，以及用于存储的浮动栅极 电子来修改晶体管的阈值电压，并且包括能够直接存储器访问（DMA）模式的电路，用于从设备外部直接访问存储器单元，通过从外部控制来将存储器单元编程为直接存储器访问模式 该器件，每个晶体管的浮置栅极存储的电荷量。

公开(公告)号：US5973966A

公开(公告)日：1999-10-26

申请号：US203798

申请日：1998-12-01

申请人： Cristiano Calligaro ,  Paolo Rolandi ,  Roberto Gastaldi ,  Guido Torelli

发明人： Cristiano Calligaro ,  Paolo Rolandi ,  Roberto Gastaldi ,  Guido Torelli

IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C11/56 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C7/062 ,  G11C11/5621 ,  G11C11/5642 ,  G11C7/065 ,  G11C7/06

摘要： A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

摘要翻译： 一种用于半导体存储器单元的读取电路，包括经由至少第一开关耦合到电源线的第一和第二有源元件，其中第一和第二有源元件分别在第一和第二电路节点连接到第一晶体管 有源元件通过它们耦合到地面。 这些第一和第二电路节点分别通过第一和第二电容元件连接到地，每个具有与电容元件并联连接的开关。