公开(公告)号：US5673221A

公开(公告)日：1997-09-30

申请号：US592939

申请日：1996-01-29

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：USRE38166E1

公开(公告)日：2003-07-01

申请号：US09410164

申请日：1999-09-30

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C1156

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m−2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：US5838612A

公开(公告)日：1998-11-17

申请号：US869072

申请日：1997-06-04

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

摘要： Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

摘要翻译： 用于多电平非易失性存储单元器件的读取电路，对于要读取的每个单元，具有与负载和去耦合和控制级相关联的选择线，其具有稳定选择线的电路节点上的电压的反馈环路 。 对该节点连接由反馈回路控制的当前复制电路。 这些包括与与存储器单元的选择线相关的负载和电路元件同源的负载和电路元件，并且具有用于连接到电流比较器电路的输出接口电路。

公开(公告)号：US5729490A

公开(公告)日：1998-03-17

申请号：US690059

申请日：1996-07-31

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C11/56 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632 ,  G11C2211/5633

摘要： A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current with a prescribed number of reference currents having values comprised between a minimum value and a maximum value of said discrete set of m cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current belongs; repeating step (a) for the sub-set of cell current values to which the cell current belongs, until the sub-set of cell current values to which the cell current belongs comprises only one cell current value, which is the value of the current of the memory cell to be sensed.

摘要翻译： 用于感测可以在多个m = 2n（n> = Z）个不同编程级别中采取一个编程电平的多级非易失性存储器单元的方法提供了在预定条件下偏置要感测的存储器单元，因此 存储器单元以具有m个不同单元电流值的离散集合的值吸收单元电流，每个单元电流值对应于所述编程电平之一。 感测方法还提供：同时将电池电流与规定数量的参考电流进行比较，所述规定数量的参考电流具有包括在所述离散的一组m个电池电流值的最小值和最大值之间的值，并且将所述离散的一组m个电池电流值 多个子单元电流子集，用于确定单元电流所属的单元电流值的子集; 对于单元电流所属的单元电流值的子集重复步骤（a），直到单元电流所属的单元电流值的子集仅包括一个单元电流值，该单元电流值是电流值 的待读取的存储单元。

公开(公告)号：US5701265A

公开(公告)日：1997-12-23

申请号：US593650

申请日：1996-01-29

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632

摘要： A serial dichotomic method for sensing multiple-level non-volatile memory cells which can take one of m=2.sup.n (n>=2) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, and for: a) comparing the cell current with a reference current which has a value comprised between a minimum value and a maximum value of said plurality of m cell current values, thus dividing said plurality of cell current values into two sub-pluralities of cell current values, and determining the sub-plurality of cell current values to which the cell current belongs; b) repeating the step a) until the sub-plurality of cell current values to which the cell current belongs comprises only one cell current value, which is the value for the current of the memory cell to be sensed.

摘要翻译： 用于感测可以采用m = 2n（n> = 2）个不同编程级中的一个的多级非易失性存储器单元的串行二分法方法提供在预定条件下偏置待感测的存储器单元，使得存储器 电池以具有多个m个不同电池电流值的值吸收电池电流，并且用于：a）将电池电流与参考电流进行比较，所述参考电流具有包含在所述多个m的最小值和最大值之间的值 电池电流值，从而将所述多个电池电流值分成两个多个电池电流值，并确定电池电流所属的电池电流值的子数量; b）重复步骤a），直到单元电流所属的单元电流值的子多个仅包含一个单元电流值，该单元电流值是要感测的存储单元的电流的值。

公开(公告)号：US5949666A

公开(公告)日：1999-09-07

申请号：US32282

申请日：1998-02-26

申请人： Vincenzo Daniele ,  Alessandro Manstretta ,  Paolo Rolandi ,  Guido Torelli

发明人： Vincenzo Daniele ,  Alessandro Manstretta ,  Paolo Rolandi ,  Guido Torelli

IPC分类号： G05F1/46 ,  H03K4/02 ,  H02M1/12 ,  G05F1/40 ,  G05F7/64

CPC分类号： G05F1/465 ,  H03K4/023

摘要： A staircase adaptive voltage generator circuit comprising a first capacitor connected between a first voltage reference and an output operational amplifier, through first and second switches, respectively. The terminals of the capacitor are also connected to a second voltage reference through third and fourth switches, respectively. A second capacitor, in series with a fifth switch, is connected in parallel to the first capacitor.

摘要翻译： 一种楼梯自适应电压发生器电路，包括分别通过第一和第二开关连接在第一电压基准和输出运算放大器之间的第一电容器。 电容器的端子也分别通过第三和第四开关连接到第二参考电压。 与第五开关串联的第二电容器与第一电容器并联连接。

公开(公告)号：US4631485A

公开(公告)日：1986-12-23

申请号：US687739

申请日：1984-12-28

申请人： Guido Torelli ,  Vincenzo Daniele

发明人： Guido Torelli ,  Vincenzo Daniele

IPC分类号： H03D1/22 ,  H03D1/06

CPC分类号： H03D1/2245

摘要： Two circuits carry out the beating of a modulated signal, with first and second signals, respectively, each having substantially the same frequency as the carrier of the modulated signal but phased-shifted relative to one another by 90.degree.. A commutator controlled by a control circuit alternately selects the signals resulting from the beating. The selection is responsive to the amplitudes of the signals in order to avoid losses of information due to amplitude peaks under a prefixed threshold which may be caused by frequency differences between the signals which are beat.

摘要翻译： 两个电路执行调制信号的跳动，第一和第二信号分别具有与调制信号的载波基本相同的频率，但相对于彼此相位相差90°。 由控制电路控制的换向器交替地选择由跳动产生的信号。 该选择响应于信号的振幅，以便避免由于可能由拍频信号之间的频率差引起的前缀阈值下的振幅峰值引起的信息损失。

公开(公告)号：US4357685A

公开(公告)日：1982-11-02

申请号：US168562

申请日：1980-07-14

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Aldo Magrucci ,  Guido Torelli

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Aldo Magrucci ,  Guido Torelli

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/32 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L29/7885 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/32 ,  H01L27/115

摘要： A nonvolatile memory of the electrically alterable kind comprises an orthogonal array of cells each including a floating-gate IGFET and an enhancement IGFET in series. For the programming or the reading of a selected cell, lying at the intersection of a row and a column of the array, a common gate lead for all the enhancement IGFETs of the row and a common drain lead for all the enhancement IGFETs of the column are energized with voltage dependent on the desired kind of operation. To write a bit in a cell, its floating gate is progressively charged in a succession of steps separated by reading operations to check on the conduction threshold of the cell; the charging ends when that threshold reaches a predetermined storage level. To cancel a written bit, the floating gate is progressively discharged in a succession of steps again separated by reading operations; the discharging is terminated when the conduction threshold reaches a predetermined cancellation level. The width and/or the amplitude of a voltage pulse applied to an accessible gate of the floating-gate IGFET during the successive charging or discharging steps may be increased after each reading step in which the desired level is not attained.

摘要翻译： 电可变类型的非易失性存储器包括每个包括浮栅IGFET和增强IGFET串联的单元的正交阵列。 对于位于阵列的行和列的交叉点处的选定单元的编程或读取，用于该行的所有增强型IGFET的公共栅极引线和用于该列的所有增强型IGFET的公共漏极引线 根据所需的操作类型而被电压通电。 为了在单元中写入一位，其浮动栅逐步地通过读取操作分离的步骤进行充电，以检查单元的导通阈值; 当该阈值达到预定的存储水平时，充电结束。 为了取消写入位，浮动栅逐步地通过读取操作分开地逐步排出; 当导通阈值达到预定的取消水平时，放电终止。 在连续充电或放电步骤中施加到浮栅IGFET的可访问栅极的电压脉冲的宽度和/或幅度可以在其中未达到期望水平的每个读取步骤之后增加。

公开(公告)号：US4992680A

公开(公告)日：1991-02-12

申请号：US456782

申请日：1989-12-27

申请人： Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

发明人： Mirella Benedetti ,  Antonio Chiriatti ,  Vincenzo Daniele ,  Biagio Giacalone

IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177 ,  H03K23/54

CPC分类号： H03K19/1735 ,  H03K19/17708 ,  H03K23/542

摘要： A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multfunctional blocks.

公开(公告)号：US6005411A

公开(公告)日：1999-12-21

申请号：US777296

申请日：1996-12-27

申请人： Vincenzo Daniele

发明人： Vincenzo Daniele

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/094

CPC分类号： H03K19/17708 ,  H03K19/1736

摘要： The present invention is a monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type, which cells allow the signal paths between signal lines of the elementary modules to be programmed and re-programmed. Preferably, the flash memory cells are Fowler-Nordheim Effect cells.

摘要翻译： 本发明是具有通过闪存类型的存储器单元电连接的基本模块的单片集成可编程器件，这些单元允许对基本模块的信号线之间的信号路径进行编程和重新编程。 优选地，闪存单元是Fowler-Nordheim Effect细胞。