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1.发明申请Transistor of the I-MOS Type Comprising Two Independent Gates and Method of Using Such a Transistor 有权包含两个独立门的I-MOS型晶体管和使用这种晶体管的方法公开(公告)号：US20090096028A1
公开(公告)日：2009-04-16
申请号：US12085866
申请日：2006-12-01
IPC分类号： H01L27/088
CPC分类号： H01L27/1057 , H01L29/7391
摘要： The transistor comprises a source (1) and a drain (2) separated by a lightly doped intermediate zone (I). The intermediate zone (I) forms first (3) and second (4) junctions respectively with the source (1) and with the drain (2). The transistor comprises a first gate (5) to generate an electric field in the intermediate zone (I), on the same side as the first junction (3), and a second gate (6) to generate an electric field in the intermediate zone (I), on the same side as the second junction (4).
摘要翻译： 晶体管包括由轻掺杂中间区（I）分离的源（1）和漏极（2）。 中间区域（I）分别与源极（1）和漏极（2）形成第一（3）和第二（4）结。 晶体管包括在与第一结（3）相同的一侧在中间区（I）中产生电场的第一栅极（5）和在中间区域中产生电场的第二栅极（6） （I），与第二结（4）相同。
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2.发明授权Transistor of the I-MOS type comprising two independent gates and method of using such a transistor 有权包括两个独立栅极的I-MOS型晶体管和使用这种晶体管的方法公开(公告)号：US07732282B2
公开(公告)日：2010-06-08
申请号：US12085866
申请日：2006-12-01
IPC分类号： H01L21/00
CPC分类号： H01L27/1057 , H01L29/7391
摘要： The transistor comprises a source and a drain separated by a lightly doped intermediate zone. The intermediate zone forms first and second junctions respectively with the source and with the drain. The transistor comprises a first gate to generate an electric field in the intermediate zone, on the same side as the first junction, and a second gate to generate an electric field in the intermediate zone, on the same side as the second junction.
摘要翻译： 晶体管包括由轻掺杂的中间区分隔开的源极和漏极。 中间区域分别与源极和漏极形成第一和第二结。 所述晶体管包括第一栅极，用于在与所述第一接合部相同的一侧产生所述中间区域中的电场，以及在与所述第二接合部相同的一侧在所述中间区域中产生电场的第二栅极。
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3.发明申请公开(公告)号：US20070170471A1
公开(公告)日：2007-07-26
申请号：US11654660
申请日：2007-01-18
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L21/8221
摘要： The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.
摘要翻译： 三维集成CMOS电路形成在混合基板中。 在具有（100）取向的第一半导体硅层中，在底层形成n-MOS型晶体管，该层可以是张力应变的。 在顶级，在具有（110）取向的锗的优选单晶和压缩应变的第二半导电层中形成p-MOS晶体管。 第二半导电层被转移到其中预先形成n-MOS晶体管的第一块，然后形成p-MOS晶体管。
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4.发明授权公开(公告)号：US07763915B2
公开(公告)日：2010-07-27
申请号：US11654660
申请日：2007-01-18
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L21/8221
摘要： The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.
摘要翻译： 三维集成CMOS电路形成在混合基板中。 在具有（100）取向的第一半导体硅层中，在底层形成n-MOS型晶体管，该层可以是张力应变的。 在顶级，在具有（110）取向的锗的优选单晶和压缩应变的第二半导电层中形成p-MOS晶体管。 第二半导电层被转移到其中预先形成n-MOS晶体管的第一块，然后形成p-MOS晶体管。
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公开(公告)号：US07579226B2
公开(公告)日：2009-08-25
申请号：US11211255
申请日：2005-08-19
申请人： Jean-Charles Barbe , Maud Vinet , Olivier Faynot
发明人： Jean-Charles Barbe , Maud Vinet , Olivier Faynot
IPC分类号： H01L21/00
CPC分类号： H01L21/26586
摘要： A method is provided for fabricating a thin layer element, in which a layer of a first material supports a pattern of a second material having a thickness of less than 15 nm, including a step of doping by implanting a chemical species over at least a portion of the layer-pattern assembly to stabilize the pattern on the layer.
摘要翻译： 提供了一种用于制造薄层元件的方法，其中第一材料层支撑厚度小于15nm的第二材料的图案，包括通过在至少一部分上植入化学物质来掺杂的步骤 的层图案组件以使层上的图案稳定。
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6.发明申请公开(公告)号：US20050136655A1
公开(公告)日：2005-06-23
申请号：US10741489
申请日：2003-12-19
IPC分类号： H01L21/335 , H01L21/44 , H01L29/76
CPC分类号： B82Y10/00 , H01L29/66439 , H01L29/7613 , Y10S438/962
摘要： The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a silicon substrate (105), the thinned region (110) offset by a non-selected region (115). The method also includes forming at least one quantum island (145) from the thinned region (110) by subjecting the thinned region (110) to an annealing process. The non-selected region (115) is aligned with the quantum island (145) and tunnel junctions (147) are formed between the quantum island (145) and the non-selected region (115). The present invention also includes a single-electron device (200), and a method of manufacturing an integrated circuit (300) that includes a single-electron device (305).
摘要翻译： 本发明提供一种制造单电子晶体管器件（100）的方法。 该方法包括在硅衬底（105）中形成减薄区域（110），所述稀疏区域（110）由非选择区域（115）偏移。 该方法还包括通过使稀化区域（110）进行退火处理从而从减薄区域（110）形成至少一个量子岛（145）。 非选择区域115与量子岛145对准，并且在量子岛145和非选择区115之间形成隧道结147。 本发明还包括单电子器件（200）和制造包括单电子器件（305）的集成电路（300）的方法。
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7.发明申请Combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI)devices 有权组合的完全耗尽的绝缘体上硅（FD-SOI）和部分耗尽的绝缘体上硅（PD-SOI）器件公开(公告)号：US20060128074A1
公开(公告)日：2006-06-15
申请号：US11010849
申请日：2004-12-13
申请人： Howard Tigelaar , Gabriel Barna , Olivier Faynot
发明人： Howard Tigelaar , Gabriel Barna , Olivier Faynot
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78612
摘要： A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110).
摘要翻译： 公开了一种在集成电路器件（2）中的单个管芯上形成完全耗尽（90）和部分耗尽的（92）绝缘体上硅（SOI）器件的方法（100） 6，8）和选择性外延生长工艺（110）。
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8.发明申请公开(公告)号：US20070007596A1
公开(公告)日：2007-01-11
申请号：US11530254
申请日：2006-09-08
IPC分类号： H01L27/12
CPC分类号： B82Y10/00 , H01L29/66439 , H01L29/7613 , Y10S438/962
摘要： The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a silicon substrate (105), the thinned region (110) offset by a non-selected region (115). The method also includes forming at least one quantum island (145) from the thinned region (110) by subjecting the thinned region (110) to an annealing process. The non-selected region (115) is aligned with the quantum island (145) and tunnel junctions (147) are formed between the quantum island (145) and the non-selected region (115). The present invention also includes a single-electron device (200), and a method of manufacturing an integrated circuit (300) that includes a single-electron device (305).
摘要翻译： 本发明提供一种制造单电子晶体管器件（100）的方法。 该方法包括在硅衬底（105）中形成减薄区域（110），所述稀疏区域（110）由非选择区域（115）偏移。 该方法还包括通过使稀化区域（110）进行退火处理从而从减薄区域（110）形成至少一个量子岛（145）。 非选择区域115与量子岛145对准，并且在量子岛145和非选择区115之间形成隧道结147。 本发明还包括单电子器件（200）和制造包括单电子器件（305）的集成电路（300）的方法。
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公开(公告)号：US20060060846A1
公开(公告)日：2006-03-23
申请号：US11211255
申请日：2005-08-19
申请人： Jean-Charles Barbe , Maud Vinet , Olivier Faynot
发明人： Jean-Charles Barbe , Maud Vinet , Olivier Faynot
IPC分类号： H01L29/02 , H01L21/425
CPC分类号： H01L21/26586
摘要： A method is provided for fabricating a thin layer element, in which a layer of a first material supports a pattern of a second material having a thickness of less than 15 nm, including a step of doping by implanting a chemical species over at least a portion of the layer-pattern assembly to stabilize the pattern on the layer.
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