公开(公告)号：US09170278B2

公开(公告)日：2015-10-27

申请号：US14273200

申请日：2014-05-08

Applicant: D-Wave Systems Inc.

Inventor： Richard David Neufeld

IPC: G01R1/067 ,  B82Y10/00 ,  G06N99/00

CPC classification number: G06N99/002 ,  B82Y10/00 ,  G01R1/06755 ,  G06F15/82 ,  G06F17/5009 ,  H01L39/025 ,  H01L39/223

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract translation: 系统可以包括彼此交叉的第一和第二量子位和具有包围第一和第二量子位的部分的至少一部分的周边的第一耦合器，第一耦合器可操作以铁磁或反铁磁耦合第一和第二量子位 第二个量子在一起 多层计算机芯片可以包括布置在第一金属层中的第一多个N个量子位，至少部分地布置在第二金属层中的第二多个量子位，该第二金属层跨越第一多个量子位的每个量子位 以及至少部分地包围来自第一和第二多个量子位的相应的一对量子比特彼此交叉的区域的第一多个N倍M个耦合器件。

公开(公告)号：US20140329687A1

公开(公告)日：2014-11-06

申请号：US14273200

申请日：2014-05-08

Applicant: D-Wave Systems Inc.

Inventor： Paul Bunyk ,  Richard David Neufeld ,  Felix Maibaum

IPC: G01R1/067

CPC classification number: G06N99/002 ,  B82Y10/00 ,  G01R1/06755 ,  G06F15/82 ,  G06F17/5009 ,  H01L39/025 ,  H01L39/223

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract translation: 系统可以包括彼此交叉的第一和第二量子位和具有包围第一和第二量子位的部分的至少一部分的周边的第一耦合器，第一耦合器可操作以铁磁或反铁磁耦合第一和第二量子位 第二个量子在一起 多层计算机芯片可以包括布置在第一金属层中的第一多个N个量子位，至少部分地布置在第二金属层中的第二多个量子位，该第二金属层跨越第一多个量子位的每个量子位 以及至少部分地包围来自第一和第二多个量子位的相应的一对量子比特彼此交叉的区域的第一多个N倍M个耦合器件。

公开(公告)号：US09634224B2

公开(公告)日：2017-04-25

申请号：US14600962

申请日：2015-01-20

Applicant: D-Wave Systems Inc.

Inventor： Eric Ladizinsky ,  Nicolas Ladizinsky ,  Jason Yao ,  Byong Hyop Oh ,  Richard David Neufeld

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/22

CPC classification number: H01L39/2493 ,  H01L27/18 ,  H01L39/223

Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.

公开(公告)号：US20150236235A1

公开(公告)日：2015-08-20

申请号：US14600962

申请日：2015-01-20

Applicant: D-Wave Systems Inc.

Inventor： Eric Ladizinsky ,  Nicolas Ladizinsky ,  Jason Yao ,  Byong Hyop Oh ,  Richard David Neufeld

IPC: H01L39/12 ,  H01L39/22 ,  H01L39/24 ,  H01L39/02

CPC classification number: H01L39/2493 ,  H01L27/18 ,  H01L39/223

Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.

Abstract translation: 一方面，制造具有约瑟夫逊结的超导集成电路包括将氧或氮施加到由外部超导层形成的结构的至少一部分，以钝化去除外部超导层的部分留下的伪影（如果有的话）。 在另一方面，沉积第一超导层，在第一超导层上沉积第二超导层，在第一超导层上形成氧化物层，在氧化物层上沉积介电层，介电层的一部分 ，去除氧化物层的第一部分，形成第二氧化物部分代替氧化物层的第一部分，并且在介电层和第二氧化物部分上沉积第三超导层。