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公开(公告)号：US11930721B2
公开(公告)日：2024-03-12
申请号：US16870537
申请日：2020-05-08
申请人： D-WAVE SYSTEMS INC.
IPC分类号： H10N60/01 , B82Y10/00 , H01L21/285 , H01L21/768 , H10N60/10 , H10N60/12 , H10N60/80 , H10N60/85 , H10N69/00 , G06N10/00
CPC分类号： H10N60/0912 , B82Y10/00 , H01L21/2855 , H01L21/76877 , H01L21/76891 , H10N60/01 , H10N60/0156 , H10N60/10 , H10N60/12 , H10N60/805 , H10N60/855 , H10N69/00 , G06N10/00
摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US10700256B2
公开(公告)日：2020-06-30
申请号：US15679963
申请日：2017-08-17
申请人： D-WAVE SYSTEMS INC.
IPC分类号： H01L39/24 , H01L27/18 , H01L39/22 , H01L21/285 , H01L39/02 , H01L39/12 , B82Y10/00 , H01L21/768 , G06N10/00
摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US20200274050A1
公开(公告)日：2020-08-27
申请号：US16870537
申请日：2020-05-08
申请人： D-WAVE SYSTEMS INC.
IPC分类号： H01L39/24 , B82Y10/00 , H01L27/18 , H01L39/22 , H01L21/285 , H01L21/768 , H01L39/02 , H01L39/12
摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US09634224B2
公开(公告)日：2017-04-25
申请号：US14600962
申请日：2015-01-20
申请人： D-Wave Systems Inc.
CPC分类号： H01L39/2493 , H01L27/18 , H01L39/223
摘要： In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.
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公开(公告)号：US20150236235A1
公开(公告)日：2015-08-20
申请号：US14600962
申请日：2015-01-20
申请人： D-Wave Systems Inc.
CPC分类号： H01L39/2493 , H01L27/18 , H01L39/223
摘要： In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.
摘要翻译： 一方面，制造具有约瑟夫逊结的超导集成电路包括将氧或氮施加到由外部超导层形成的结构的至少一部分，以钝化去除外部超导层的部分留下的伪影（如果有的话）。 在另一方面，沉积第一超导层，在第一超导层上沉积第二超导层，在第一超导层上形成氧化物层，在氧化物层上沉积介电层，介电层的一部分 ，去除氧化物层的第一部分，形成第二氧化物部分代替氧化物层的第一部分，并且在介电层和第二氧化物部分上沉积第三超导层。
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6.发明申请公开(公告)号：US20150187840A1
公开(公告)日：2015-07-02
申请号：US14589574
申请日：2015-01-05
申请人： D-Wave Systems Inc.
CPC分类号： H01L27/18 , B82Y10/00 , G06N99/002 , H01L28/24 , H01L39/025 , H01L39/223 , H01L39/2406 , H01L39/2493 , Y10S977/707 , Y10S977/723 , Y10S977/943
摘要： Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
摘要翻译： 各种技术和设备允许制造超导电路和结构，例如约瑟夫逊结，其可以例如在量子计算机中有用。 例如，可以制造具有插入在能够超导的两个元件或层之间的电介质结构或层的低磁通量噪声三层结构。 超导通孔可以直接覆盖约瑟夫逊结。 诸如约瑟夫逊结的结构可以承载在平坦化的电介质层上。 可以使用翅片来除去结构中的热量。 能够超导的通孔可以具有小于约1微米的宽度。 该结构可以例如通过通孔和/或带连接器耦合到电阻器。
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公开(公告)号：US20150119252A1
公开(公告)日：2015-04-30
申请号：US14383837
申请日：2013-03-07
申请人： D-Wave Systems Inc.
CPC分类号： H01L39/2493 , B82Y10/00 , G06N99/002 , H01L27/18 , H01L39/025 , H01L39/125 , H01L39/22 , H01L39/223 , H01L39/24 , H01L39/2406
摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
摘要翻译： 各种技术和装置允许制造超导电路。 可以形成铌/氧化铝/铌三层，并形成单个的约瑟夫逊结（JJ）。 保护盖可以在制造过程中保护JJ。 可以形成混合电介质。 可以使用减法图案化和/或添加剂图案化来形成超导集成电路。 可以通过电镀和/或通过化学机械平面化抛光来沉积超导金属层。 内层电介质的厚度可以通过沉积工艺来控制。 衬底可以包括硅的基底和包括氧化铝的顶层。 可以停止或暂停超导金属层的沉积，以在完成之前进行冷却。 可以通过在超导金属层中图案化对准标记物来对准多个层。
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公开(公告)号：US11856871B2
公开(公告)日：2023-12-26
申请号：US17681303
申请日：2022-02-25
申请人： D-WAVE SYSTEMS INC.
发明人： Trevor M. Lanting , Danica W. Marsden , Byong Hyop Oh , Eric G. Ladizinsky , Shuiyuan Huang , J. Jason Yao , Douglas P. Stadtler
CPC分类号： H10N60/805 , G06N10/00 , H10N60/0156 , H10N60/0912 , H10N60/12 , H10N69/00
摘要： Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.
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公开(公告)号：US20180219150A1
公开(公告)日：2018-08-02
申请号：US15503367
申请日：2015-08-12
申请人： D-Wave Systems Inc.
IPC分类号： H01L39/24 , H01L39/22 , H01L21/768
CPC分类号： H01L39/2493 , H01L21/76891 , H01L23/53285 , H01L27/18 , H01L39/223
摘要： Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.
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公开(公告)号：US20180033944A1
公开(公告)日：2018-02-01
申请号：US15679963
申请日：2017-08-17
申请人： D-WAVE SYSTEMS INC.
CPC分类号： H01L39/2493 , B82Y10/00 , G06N10/00 , H01L21/2855 , H01L21/76877 , H01L21/76891 , H01L27/18 , H01L39/025 , H01L39/125 , H01L39/22 , H01L39/223 , H01L39/24 , H01L39/2406
摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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