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    PERFORMING NON-PREFERRED DIRECTION DETAILED ROUTING FOLLOWED BY PREFERRED DIRECTION GLOBAL AND DETAILED ROUTING
    4.
    发明公开
    PERFORMING NON-PREFERRED DIRECTION DETAILED ROUTING FOLLOWED BY PREFERRED DIRECTION GLOBAL AND DETAILED ROUTING 审中-公开

    公开(公告)号：US20230274068A1

    公开(公告)日：2023-08-31

    申请号：US18110338

    申请日：2023-02-15

    Applicant: D2S, Inc.

    Inventor： Akira Fujimura

    IPC: G06F30/3947

    CPC classification number: G06F30/3947

    Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

    CONCURRENTLY ROUTING MULTIPLE PARTITIONS OF AN INTEGRATED CIRCUIT DESIGN
    5.
    发明公开
    CONCURRENTLY ROUTING MULTIPLE PARTITIONS OF AN INTEGRATED CIRCUIT DESIGN 审中-公开

    公开(公告)号：US20230274066A1

    公开(公告)日：2023-08-31

    申请号：US18110346

    申请日：2023-02-15

    Applicant: D2S, Inc.

    Inventor： Akira Fujimura

    IPC: G06F30/394

    CPC classification number: G06F30/394

    Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

    COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS
    6.
    发明公开
    COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS 审中-公开

    公开(公告)号：US20230186009A1

    公开(公告)日：2023-06-15

    申请号：US17889370

    申请日：2022-08-16

    Applicant: D2S, Inc.

    Inventor： Akira Fujimura ,  Nagesh Shirali ,  Donald Oriordan

    IPC: G06F30/3953 ,  G06T7/00 ,  G06F30/398 ,  G06N3/045 ,  G06F30/392 ,  G06F30/27

    CPC classification number: G06F30/3953 ,  G06T7/0006 ,  G06F30/398 ,  G06N3/045 ,  G06F30/392 ,  G06F30/27 ,  G06T7/0004 ,  G06F2119/10

    Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

    COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS
    7.
    发明申请
    COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS 有权

    公开(公告)号：US20230032510A1

    公开(公告)日：2023-02-02

    申请号：US17889373

    申请日：2022-08-16

    Applicant: D2S, Inc.

    Inventor： Akira Fujimura ,  Nagesh Shirali ,  Donald Oriordan

    IPC: G06F30/398 ,  G06F30/27 ,  G06F30/392 ,  G06T7/00

    Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

    METHOD AND SYSTEM FOR FORMING A PATTERN ON A SURFACE USING MULTI-BEAM CHARGED PARTICLE BEAM LITHOGRAPHY
    8.
    发明申请
    METHOD AND SYSTEM FOR FORMING A PATTERN ON A SURFACE USING MULTI-BEAM CHARGED PARTICLE BEAM LITHOGRAPHY 审中-公开

    公开(公告)号：US20190237299A1

    公开(公告)日：2019-08-01

    申请号：US16380890

    申请日：2019-04-10

    Applicant: D2S, Inc.

    Inventor： Akira Fujimura

    IPC: H01J37/317

    CPC classification number: H01J37/3175 ,  H01J37/3177

    Abstract: A method for fracturing or mask data preparation is disclosed in which a plurality of single-beam charged particle beam shots is used to create a plurality of multi-beam shots, where multi-beam exposure information is determined for each of the single-beam shots, and then the resulting multi-beam exposure information is used to generate a set of multi-beam shots. Additionally, a method for fracturing or mask data preparation is disclosed in which a plurality of single-beam shots is used to generate a set of multi-beam shots by calculating an image which the single-beam shots would form on a surface.

    METHOD AND SYSTEM FOR FORMING PATTERNS USING SHAPED BEAM LITHOGRAPHY INCLUDING TEMPERATURE EFFECTS
    9.
    发明申请
    METHOD AND SYSTEM FOR FORMING PATTERNS USING SHAPED BEAM LITHOGRAPHY INCLUDING TEMPERATURE EFFECTS 审中-公开

    公开(公告)号：US20170124247A1

    公开(公告)日：2017-05-04

    申请号：US15298464

    申请日：2016-10-20

    Applicant: D2S, Inc.

    Inventor： Akira Fujimura ,  Harold Robert Zable ,  Ryan Pearman ,  William Guthrie

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  H01J37/3026 ,  H01J37/3174 ,  H01J2237/31771 ,  H01J2237/31774

    Abstract: In some embodiments, data is received defining a plurality of shot groups that will be delivered by a charged particle beam writer during an overall time period, where a first shot group will be delivered onto a first designated area at a first time period. A temperature of the first designated area at a different time period is determined. In some embodiments, the different time period is when secondary effects of exposure from a second shot group are received at the first designated area. In some embodiments, transient temperatures of a target designated area are determined at time periods when exposure from a shot group is received. An effective temperature of the target area is determined, using the transient temperatures and applying a compensation factor based on an amount of exposure received during that time period. A shot in the target shot group is modified based on the effective temperature.

    Method for fracturing and forming a pattern using shaped beam charged particle beam lithography
    10.
    发明授权
    Method for fracturing and forming a pattern using shaped beam charged particle beam lithography 有权
    使用成形束带电粒子束光刻法压裂和形成图案的方法

    公开(公告)号：US09448473B2

    公开(公告)日：2016-09-20

    申请号：US14970505

    申请日：2015-12-15

    Applicant: D2S, Inc.

    Inventor： Akira Fujimura ,  Michael Tucker

    IPC: G03F1/70 ,  G03F1/78 ,  G03F7/20 ,  G06F17/50 ,  H01J37/317 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/302

    CPC classification number: G03F1/78 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/68 ,  G03F1/70 ,  G03F7/2061 ,  G06F17/5045 ,  G06F17/5081 ,  H01J37/3026 ,  H01J37/3174 ,  H01J2237/31774 ,  Y10S430/143

    Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, where a non-circular target pattern to be formed on a surface is input. A plurality of charged particle beam shots for a multi-beam charged particle beam system is determined, where the plurality of shots will form a pattern on the surface, each charged particle beam shot being a multi-beam shot comprising a plurality of circular or nearly-circular beamlets. The pattern on the surface matches the target pattern within a predetermined tolerance. The determining is performed using a computing hardware device.

    Abstract translation: 在使用带电粒子束光刻的半导体制造领域中，公开了一种用于压裂或掩模数据准备或邻近效应校正的方法和系统，其中输入要在表面上形成的非圆形目标图案。 确定用于多光束带电粒子束系统的多个带电粒子束射击，其中多个射击将在表面上形成图案，每个带电粒子束被射出为包括多个圆形或近似 圆形小梁。 表面上的图案与预定公差内的目标图案相匹配。 使用计算硬件设备执行确定。

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