公开(公告)号：US20230361776A1

公开(公告)日：2023-11-09

申请号：US17736517

申请日：2022-05-04

申请人： DANIEL RYAN WALLACE ,  MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI

发明人： DANIEL RYAN WALLACE ,  MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI

IPC分类号： H03K19/195 ,  H03K19/20 ,  H03K19/17736 ,  H03K3/38

CPC分类号： H03K19/195 ,  H03K19/20 ,  H03K19/17744 ,  H03K19/1774 ,  H03K3/38

摘要： Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

公开(公告)号：US20230360712A1

公开(公告)日：2023-11-09

申请号：US17736564

申请日：2022-05-04

申请人： ALEXANDER LOUIS BRAUN ,  MAX E. NIELSEN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI ,  CHARLES RYAN WALLACE

发明人： ALEXANDER LOUIS BRAUN ,  MAX E. NIELSEN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI ,  CHARLES RYAN WALLACE

IPC分类号： H03L7/081 ,  H03L7/08 ,  H03K19/195 ,  H03K3/037

CPC分类号： H03L7/0816 ,  H03L7/0805 ,  H03K19/195 ,  H03K3/037

摘要： Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

公开(公告)号：US20230363292A1

公开(公告)日：2023-11-09

申请号：US17736463

申请日：2022-05-04

申请人： MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI ,  CHARLES R. WALLACE

发明人： MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  HAITAO O. DAI ,  CHARLES R. WALLACE

IPC分类号： G06N10/40 ,  H01L39/22

CPC分类号： H01L39/223 ,  G06N10/40

摘要： Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson transmission lines (JTLs) or logic gates having strengthened or weakened bias taps as compared to bias taps of JTLs or logic gates in the operational RQL circuitry. Sampler JTLs or logic gates with weakened bias taps to AC clock resonators can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. Staging relative strengths of the bias taps of the samplers in an ensemble of samplers allows for outputs of wrapper circuitry to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range.

公开(公告)号：US20230359915A1

公开(公告)日：2023-11-09

申请号：US17736646

申请日：2022-05-04

申请人： HAITAO O. DAI ,  MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  CHARLES RYAN WALLACE

发明人： HAITAO O. DAI ,  MAX E. NIELSEN ,  ALEXANDER LOUIS BRAUN ,  DANIEL GEORGE DOSCH ,  KURT PLEIM ,  CHARLES RYAN WALLACE

IPC分类号： G06N10/40 ,  G01R33/035

CPC分类号： G06N10/40 ,  G01R33/0354

摘要： An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted.

公开(公告)号：US20220393850A1

公开(公告)日：2022-12-08

申请号：US17340814

申请日：2021-06-07

申请人： BRIAN LEE KOEHLER ,  COREY ARTHUR KEGERREIS ,  HAITAO O. DAI ,  QUENTIN P. HERR

发明人： BRIAN LEE KOEHLER ,  COREY ARTHUR KEGERREIS ,  HAITAO O. DAI ,  QUENTIN P. HERR

IPC分类号： H04L7/00 ,  H03K19/195 ,  G06N10/00 ,  G06F13/40

摘要： One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.