公开(公告)号：US10170470B2

公开(公告)日：2019-01-01

申请号：US15684057

申请日：2017-08-23

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Toru Onishi ,  Katsuhiro Kutsuki ,  Yasushi Urakami ,  Yukihiko Watanabe

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/16

Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.

公开(公告)号：US10121862B2

公开(公告)日：2018-11-06

申请号：US15662829

申请日：2017-07-28

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Yuto Kurokawa ,  Yusuke Yamashita ,  Yasushi Urakami

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A switching device includes a semiconductor substrate; first and second trenches; gate insulating layers; and gate electrodes. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, first and second bottom semiconductor regions of the second conductivity type disposed in areas extending to bottom surfaces of the first and second trenches, and a connection semiconductor region of the second conductivity type extending from the first trench to reach the second trench in a depth range from a depth of a lower end of the body region to a depth of the bottom surfaces of the first and second trenches, the connection semiconductor region contacting the second semiconductor region, and being connected to the body region, and the first and second bottom semiconductor regions.

公开(公告)号：US20150275397A1

公开(公告)日：2015-10-01

申请号：US14435335

申请日：2013-10-29

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  DENSO CORPORATION ,  SHOWA DENKO K.K.

Inventor： Itaru Gunjishima ,  Keisuke Shigetoh ,  Yasushi Urakami ,  Akihiro Matsuse

IPC: C30B29/36 ,  C30B23/02 ,  C30B25/20 ,  C30B19/12

CPC classification number: C30B29/36 ,  C30B9/00 ,  C30B19/12 ,  C30B23/025 ,  C30B25/186 ,  C30B25/20 ,  Y10T428/21

Abstract: A seed crystal for SiC single-crystal growth includes a facet formation region containing a {0001}-plane uppermost portion and n (n>=3) planes provided enclosing the periphery of the facet formation region. The seed crystal for SiC single-crystal growth satisfies the relationships represented by formula (a): Bkk-1

Abstract translation: 用于SiC单晶生长的晶种包括包含{0001}面最上部分的面形成区域和包围小面形成区域的周边的n（n> = 3）面。 用于SiC单晶生长的晶种满足式（a）表示的关系：Bkk-1 <= cos-1（sin（2.3度）/ sin Ck），式（b）：Bkk <= cos-1 sin（2.3度）/ sin Ck）和公式（c）：min（Ck）<= 20度。 在公式中，C k是第k平面的偏移角，Bkk-1是由第k平面和第（k-1）脊线的偏移下游方向限定的角度，Bkk是 由第k平面的偏移下游方向和第k条脊线限定的角度。

公开(公告)号：US10770580B2

公开(公告)日：2020-09-08

申请号：US16341340

申请日：2017-10-30

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Toru Onishi ,  Sachiko Aoi ,  Yasushi Urakami

IPC: H01L29/78 ,  H01L29/423

Abstract: In an end portion of a trench, an opening where the end portion of the trench is exposed is formed in a lead-out electrode, a side surface of the trench gate electrode on a top surface side of a semiconductor substrate is spaced from a trench side surface, and a range adjacent to a boundary line positioned between a top surface of the semiconductor substrate and the trench side surface is covered with a laminated insulating film configured such that an interlayer insulating film is laminated on a gate insulating film. This makes it possible to prevent dielectric breakdown of an insulating film.

公开(公告)号：US10374081B2

公开(公告)日：2019-08-06

申请号：US16075870

申请日：2016-12-26

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Sachiko Aoi ,  Yasushi Urakami

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L21/04 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417

Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of this element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region, and in contact with the gate insulation layer on a lower side of the body region. The bottom region includes a low concentration region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench; and a high concentration region in contact with the gate insulation layer in a second range of the bottom surface adjacent to the first range.

公开(公告)号：US20180182889A1

公开(公告)日：2018-06-28

申请号：US15816697

申请日：2017-11-17

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hidefumi Takaya ,  Yasushi Urakami ,  Yukihiko Watanabe

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66

Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.

公开(公告)号：US09048102B2

公开(公告)日：2015-06-02

申请号：US14353710

申请日：2012-12-03

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Itaru Gunjishima ,  Yasushi Urakami ,  Ayumu Adachi

IPC: H01L29/04 ,  H01L31/036 ,  C30B29/36 ,  C30B23/02 ,  H01L29/16

CPC classification number: H01L29/045 ,  C30B23/025 ,  C30B29/36 ,  H01L29/1608

Abstract: An SiC single crystal includes a low dislocation density region (A) where the density of dislocations each of which has a Burgers vector in a {0001} in-plane direction (mainly a direction parallel to a direction) is not more than 3,700 cm/cm3. Such an SiC single crystal is obtained by: cutting out a c-plane growth seed crystal of a high offset angle from an a-plane grown crystal; applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range; cutting out a c-plane growth crystal of a low offset angle from the obtained c-plane grown crystal; and applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range. An SiC wafer and a semiconductor device are obtained from such an SiC single crystal.

Abstract translation: SiC单晶包括低位错密度区域（A），其中位错密度在{0001}面内方向（主要是平行于<11-20>方向的方向）上具有汉堡矢量不是 超过3700厘米/厘米3。 这样的SiC单晶通过以下方式获得：从a平面生长的晶体切出高偏移角的c面生长晶种; 应用c面生长，使得引入c面平面的螺旋位错的密度可能落在规定的范围内; 从得到的c面生长晶体中切出低偏移角的c面生长晶体; 并施加c面生长，使得引入c面小面的螺旋位错的密度可能落在规定的范围内。 从这种SiC单晶中获得SiC晶片和半导体器件。

公开(公告)号：US10204980B2

公开(公告)日：2019-02-12

申请号：US15602741

申请日：2017-05-23

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Yoshifumi Yasuda ,  Tatsuji Nagaoka ,  Yasushi Urakami ,  Sachiko Aoi

IPC: H01L21/26 ,  H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417 ,  H01L29/872 ,  H01L29/16 ,  H01L21/04 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

Abstract: A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner circumferential guard rings; and outer circumferential guard rings having a width narrower than a width of the inner circumferential guard rings. An interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings. Each of the inner circumferential guard rings includes a first high concentration region and a first low concentration region. Each of the outer circumferential guard rings includes a second high concentration region and a second low concentration region. A width of a part of each first low concentration region that is exposed on a front surface of the semiconductor device is wider than a width of a part of each second low concentration region that is exposed on the front surface.

公开(公告)号：US10056374B2

公开(公告)日：2018-08-21

申请号：US15681822

申请日：2017-08-21

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Yasushi Urakami ,  Sachiko Aoi

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7813

Abstract: A switching device may be provided with: a semiconductor substrate; a trench provided in an upper surface of the semiconductor substrate; a gate insulating layer covering an inner surface of the trench; and a gate electrode located in the trench. The semiconductor substrate includes: a first semiconductor region being in contact with the gate insulating layer; a body region being in contact with the gate insulating layer under the first semiconductor region; a second semiconductor region being in contact with the gate insulating layer under the body region; a bottom region being in contact with the gate insulating layer at a bottom surface of the trench; and a connection region being in contact with the gate insulating layer at a lateral surface of the trench and connecting the body region and the bottom region. The connection region is thicker than the bottom region.

公开(公告)号：US11004765B2

公开(公告)日：2021-05-11

申请号：US16667111

申请日：2019-10-29

Applicant: DENSO CORPORATION

Inventor： Jun Saito ,  Yusuke Yamashita ,  Yasushi Urakami

IPC: H01L29/78 ,  H01L23/367 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L23/373 ,  H01L29/739 ,  H01L29/49

Abstract: A semiconductor device may include a semiconductor substrate, an insulator film covering a part of an upper surface of the substrate, and a gate electrode opposing the upper surface via the insulator film. In the semiconductor substrate, a drift layer extending through a body layer to the upper surface opposes the gate electrode via the insulator film. The insulator film extends from the upper surface of the semiconductor substrate to an upper surface of the gate electrode by passing between the gate electrode and an upper electrode, and defines an opening at the upper surface of the gate electrode. A side surface of the opening of the insulator film is entirely located outside a volume space consisting of all straight lines that passes through the opposing surface of the drift layer at angle of 45 degrees to the opposing surface.